Page 73 - Embedded Microprocessor Systems Real World Design
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It is  necessary to gate the I/O  strobes with  the -RD  or -WR  signals because
                the address typically is held longer than the data for a write. If  a write strobe was
                just an address decode (not gated with -WR), the register would not get a clock
                until the after data were gone. If the read strobe were not gated with -RD, an out-
                put buffer would be enabled too long, and there may  be bus contention at the
                end of the bus cycle when the next one starts and the microprocessor tries to drive
                the  data bus. A  second reason  for gating the  strobes is  that while  the  address
                is changing at the start of a bus cycle, the address lines may not all change at the
                same  time.  Consequently, the  wrong  address may  momentarily  appear  on  the
                address lines, and the wrong device could be selected. The decoding logic could
                produce a short pulse on a write strobe signal, clocking garbage data into a regis-
                ter. Gating read and write strobes with the control signals makes sure the strobes
                go  active only when  address and data signals are stable. Figure  2.13 shows this
                timing.
                  The last circuit in Figure 2.13 shows how a 22V10  (or other PLD) can be used
                to generate address decodes and read/write strobes fi-om a single IC. This example
                decodes a 16-bit (64K) address space, producing a 32K EPROM chip select from
                addresses 8000 through m, an 8K RAM chip select from 0000 through  lFFI?,
                and a peripheral chip select from 3000 through 3m. Read strobes are generated
                at 4000 and 4004, and write strobes are generated at 4000, 4001, and 4002. Since
                the  EPROM,  RAM, and  our  hypothetical peripheral  IC  have  their  own  -WE
                and -0E  inputs, the chip selects for these parts will  not be gated with the -RD
                and -WR  signals from the microprocessor. The read/write  strobes will  be gated
                with  the  control signals, however, because  they  are intended  for clocking data
                into  a  latch  or for  enabling a  buffer. The  following equations implement this
                PLD  in CUPL/AE%EL format (& is the logical AND  function, # is the logical OR
                function, a ! prefix indicates a low-true signal, and a double slash  [//I  precedes
                comments).

                   IEPROMCS  = A15; // 8000-FFF'F
                   !RAMCS = lA15  Be 1814 Be 1A13; /I 0000-1FF'F
                   !PERIPRCS = 1A15 & !A14 & A13 & A12; // 3000-3F'FF
                   !WSTBl = 1A15 & A14 & IA13  & !A12 Be lAll  & lAlO &
                   !A9 & 1A2  & IAl  Be !A0 Be IWR;  // 4000
                   IWS"B2  = !A15 & A14 & lA13 & IA12 & lAll  & lAlO  &
                   IAQ Be lA2 Be 1Al  & A0 & IWR;  // 4001
                   lWS"B3 = 1A15 Be A14 & 1A13 & IA12 Be lAll  & lAlO  &
                   IA9  Be !A2 & A1  & IAO  & !WR;  // 4002
                   !RsTBl = lA15  & A14 & IA13 Be 1A12 & lAll  & !A10 &
                   !A9 & lA2 8e  !A1 & !A0 & ID; // 4000
                   IRsTB2 = 1A15 Be A14 Be 1A13 Be IA12 & lAll Be lAlO  &
                   IAQ & A2 Be 1Al  Be IAO  & IRD;  // 4004


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