Page 68 - Embedded Microprocessor Systems Real World Design

of refreshing and the processor wants to start a read cycle? There are several ways
to handle the conflict between processor and refresh cycles:
Use wait states. If the processor wants to use the DRAM, it must wait until the
current refresh cycle is completed. This probably is the most common method
of handling refresh.
Synchronize refresh to the processor. Allow refresh to occur only for cycles
that do not use the DRAM. This can be dangerous if the processor is
executing code from the DRAM, which may never permit refresh to occur.
However, if the DRAM will be used only for data, this approach may be
feasible. A slow processor may permit the entire refresh cycle to be performed
without affecting normal operation, such as during the ALE time.
Use the direct memory access (DMA) capability of the processor. DMA can
be used for refresh by allowing the refresh logic to request a hold and do
the refresh cycle when the processor acknowledges the hold request. The
disadvantage of this is that it usually takes a few clocks for the processor to get
in and out of hold.
Use built-in refresh. Many microprocessors, such as some versions of the
80C186, have built-in refresh logic. This consists of an internal timer that
generates refresh requests at regular intervals. Processors that generate refresh
requests internally also provide the refresh row address, so that -RASonly
refresh cycles may be performed.
If the internal refresh capability of the DRAM is to be used, the DRAM timing
logic must detect the refresh condition and generate the Wbefore-RAS cycle.
DRAM timing logic may be implemented using discrete logic or programmable
logic devices (PLDs) . The required delays may be generated using delay lines or a
clock. Either way, all the DRAM timing constraints must be met. Probably the most
common mistakes in DRAM design are failing to meet the setup/hold times and
failing to meet the precharge times, especially when switching between refresh and
processor access to the part.
Some memory ICs, such as the Toshiba TC59LM814, have a self-refresh capa-
bility. This function handles all the timing, addressing, and control necessary to
refresh the memory. The only drawback is that the CPU cannot access the memory
while refreshing, and the CPU must command the self-refresh to begin. The
TC59LM814 has two control bits that select self-refresh and other modes of
operation.

DRAM Controller ICs If you do not want to roll your own timing logic, a number
of controller ICs simpl@ the task of interfacing to and controlling DRAMS. Typical
examples are the DP8421 and DP8422 from National Semiconductor. Some pro-
grammable logic vendors also have FPGA-based designs for DRAM controllers.

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