Page 67 - Embedded Microprocessor Systems Real World Design

When -DS goes inactive, -CAS is removed immediately. The DRAM drives the
data bus as long as -CAS is active, so allowing the -CAS inactive state to propagate
through the delays could cause bus contention. The delays in Figure 2.11 may be
implemented with delay lines or synchronous logic. In either case, you must make
sure that the inactive state of -DS has propagated through all delays before the
next cycle starts. This circuit is simplified since it does not include a provision for
separate refresh, but it shows the timing principles involved.
Because DRAM has two address setup/hold times and two address strobes in one
cycle, it is slower than equivalent SRAM parts. The example in Figure 2.11 did not
start the DRAM cycle until the data strobe from the processor occurred. This may
require the addition of wait states, depending on processor and DRAM speed. In
some designs, you can start the cycle early. On Intel-type processors, the -W signal
can be generated when ALE goes active. With a Motorola-type bus, the address
strobe can be used to start the cycle. In both cases, the address decoding must be
fast enough to ensure that the RAM is not falsely selected. Also, the address multi-
plexer adds an additional level of delay that must be taken into account; the row
address must be stable prior to the leading edge of -RAS.

Refresh Dynamic RAM must be refreshed. The storage capacitor loses its charge
fairly quickly, typically in 15 milliseconds (ms) or less. Refresh is accomplished by
accessing each row in the DRAM. Internal logic in the DRAM restores the charge
on the capacitor. Note that accessing any row refreshes all columns in that row. For
example, a 256K DRAM typically has 256 rows and 1024 columns. Any read or write
cycle refreshes the entire row, but the catch is that allrows (that is, all row addresses)
must be refreshed within the refresh interval.
Unless refresh was accomplished with an actual data read, early DRAMS required
that the user generate a refresh address and a -RAS signal every 15 microseconds
(ps) or so. On a 256K DRAM, this refreshes all 256 rows in about 4ms. This scheme
required an external counter and a way to multiplex the count onto the address
lines. The timing logic had to recognize a refresh request and generate a refresh
cycle, arbitrating it with processor cycles. Newer DRAMS can still use this -RASonly
refresh, but they make refresh easier by also supplying an internal refresh address
counter. Each time the DRAM is refreshed using a special refresh cycle, the counter
increments to the next address.
The internal refresh cycle is started by reversing the order of -CAS and -RAS.
-CAS is driven low first, followed by -W. The DRAM recognizes this condition
and refreshes the internal row, then increments the refresh counter. The data bus
is not driven during the refresh cycle.
While an external counter is not required for the internal refresh cycle, refresh
still poses some problems. First, an external timer must generate a request for
refresh at regular intervals. Second, the interface logic must interleave the refresh
cycles with the processor access cycles. What happens if the DRAM is in the middle

52 Embe&d Microprocessor Systems