Page 63 - Embedded Microprocessor Systems Real World Design

Tdsr = Tdsm - Td
where Tdsr is the data setup time required by your RAM; Tdsm is the data setup
time, before the trailing edge of -WR, provided by the microprocessor; and Td
represents any delays in the data path, such as a data bus buffer.
Data and address hold time are calculated by determining how long the micro-
processor holds the address and data after the trailing edge of -WR. If you use
address latches for all address lines, address hold time usually will not be a problem
since the address will remain stable until the start of the next cycle. If you have data
bus buffers, add the minimum propagation delay, if known, to the microprocessor
data hold time. If the minimum is not known, do not add the buffer delay. If there
are delays in the -WR path, subtract those, as they delay removal of -WR from the
RAM. The RAM must have a smaller hold time requirement than the calcu-
lated result:

Tholdr = Tholdm + Td
where Tholdr is the data hold time required for RAM; Tholdm is the data hold
time provided by microprocessor; and Td is the minimum data bus propagation
delay (if known) plus delays in the -WR path (if any).
The preceding information is based on the assumption that your microproces-
sor generates separate -RD and -WR signals. For microprocessors, such as the 28
family, that generate a data strobe and an R/W signal, there are two options: First,
the -0E pin on the RAM is grounded and the -WE signal is connected to R/W.
One of the chip select signals is connected to the data strobe from the processor.
The -WE signal on a static RAM overrides the -0E signal, permitting a write cycle
to occur even if the -0E signal is low. The disadvantage to this is that the output
enable time becomes the chip select access time, which may require that a faster
device be used.
The second option for these processors is to generate the read and write strobes
from the microprocessor data strobe and direction signals. Figure 2.9 shows a
typical circuit for doing this.

Nonvolatile RAM

As mentioned earlier, NVRAM usually is an SRAM with a battery and power switch-
ing logic added. It has the same timing parameters as SRAM and is interfaced in
the same way.

Dynamic RAM
Dynamic RAM, as mentioned earlier, stores information as a charge on a capacitor.
DRAM is less common in embedded designs than is static RAM and typically is used
where a lot of memory is needed. Because a DRAM memory cell consists of a capac-

48 Embedded Microprocessor Systems