Page 59 - Embedded Microprocessor Systems Real World Design

A processor with a nonmultiplexed data bus will have different timing from
that shown in Figure 2.6, but the basic concepts are the same. The processor will
assert the address some delay after a clock edge, a control strobe will generate some
delay after another clock edge, and the processor will want data to be stable on the
rising edge of the control strobe or on the clock edge preceding it. The EPROM
must be fast enough to produce data in the time from when the address is
stable to when the processor needs the data, minus any delays in the data or ad-
dress paths.
For most EPROMs, the access time from chip select is the same, or nearly the
same, as the access time from the address. Referring again to Figure 2.6, the
EPROM chip select is generated by address decoding logic. The procedure for cal-
culating the chip select access time is the same as for the address access time except
that the delay through the address decode logic must be subtracted from the total
time available. If the upper address bits are latched and then decoded to generate
the chip select, both the latch delay and the decoder delay must be subtracted from
the total time. After the address and chip select access times are calculated, the
EPROM speed required is the smaller of the two numbers.
The next EPROM parameter is the output enable time. This is the time from
when the microprocessor asserts the -RD strobe (or the equivalent signal) to when
it needs stable data available. In most cases, an EPROM selected to meet the
address/chip select access time will not cause a problem with the output enable
time. However, it should be checked. Calculating the output enable time is similar
to calculating the access time:
Calculate the time from when the microprocessor asserts the -RD signal until
it requires stable data.
Subtract any delays, such as the data bus transceivers.
The result is the required EPROM output enable, which can be expressed in
equation form like this:
Toee = Toem - Td

where Toee is the required output enable time of the EPROM; Toem is the
time from when the microprocessor asserts -RD until it needs stable data; and
Td is the sum of any circuit delays, such as gating logic in the -RD signal or
data bus buffers.

The last parameter is the EPROM data hold time. This is the time from when
the output enable (OE) signal goes high until the EPROM actually stops driving
(tristating) its pins, sometimes called the datu bus reZeuse tim. This time is impor-
tant because if the EPROM is still driving the data bus when the processor starts
the next cycle, there will be bus contention and the wrong address can be latched.
In most cases, selecting an EPROM that is fast enough for the processor also results

44 Embedded Micrwocessar Systems