Page 60 - Embedded Microprocessor Systems Real World Design

in the data hold time being fast enough. However, when a very fast processor is
interfaced to a slow EPROM, the hold time can be a problem. If the calculated hold
time is a problem, the solution is to use a data buffer (more about that later) or
go to a faster EPROM.
Calculating the timing for flash memories is the same as for EPROMs except that
you also must take into account the write timing. In this respect, flash memory
timing is similar to a RAM, which we will discuss next.

RAM

Two general types of RAM are used in embedded systems. The first and most
common is static RAM (SRAM). Static means that the memory cells do not change
unless they are rewritten or the power is removed. A static RAM consists of an array
of flip-flops that are selected by a decoding array inside the chip. Static RAM usually
comes in x8 configurations, but there are some x16 devices.
A special case of static RAM is nonvolatile RAM (NVRAM). This consists of a
special low-power RAM chip packaged with a battery (usually lithium). The com-
bination also includes power-switching circuitry that operates the RAM from system
power when available and from the battery when system power is removed. The
switching logic also protects the RAM from inadvertent writes when the power
is below a certain threshold, usually when the system power is coming on or
going off.
The other type of RAM is dynamic RAM (DRAM). Dynamic RAM is used in per-
sonal computers (PCs). It stores information as charge on a tiny capacitor, one per
data bit. Because the capacitor charge bleeds off, the data must be refreshed
periodically. DRAM multiplexes the address pins into row and column addresses.
The row address is latched in with a signal called RAS (row address strobe), and
the column address is latched in with a signal called CAS (column address strobe).
The need to multiplex the addresses, generate the strobes, and refresh the
part make DRAM more difficult to design with. Dynamic RAM can be made smaller
than static RAM, so a single DRAM chip will be denser than a corresponding static
RAM chip.

Calculating RAM Access Time
Figure 2.7 shows an SRAM IC connected to a microprocessor with a multiplexed
addreddata bus. Note that the connections are identical to those for an EPROM
with the exception of the added write enable signal, which is connected to the
microprocessor -WR signal. Although not shown, some RAM ICs have multiple chip
select inputs.

Hardware Design I 45