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124 CHAPTER 3 / BACKGROUND FOR DIGITAL DESIGN
if Betty is not present at the dance. David will dance only with Betty. Obtain the logic
expression representing the active state of dancing for A, B, C, and D.
3.14 Use a minimum number of gates and inverters to implement the functions below
with NAND/INV logic. Give the gate/input tally for each logic circuit, excluding in-
verters. Implement the function exactly as presented — make no alterations. Assume
that all inputs arrive from positive logic sources. Use the inverters for logic level
conversion.
(a) Z(ff) = (XY
(b) F(H) = [AD + (B
(c) g(L) = (wy + x+ z)(L)
(d) G(L) = [(AB + C)£)](L )
(e)
3.15 Repeat Problem 3.14 by using NOR/INV logic. Assume that all inputs arrive from
positive logic sources.
3.16 Repeat Problem 3. 14 by using AND/OR/INV logic. Assume that all inputs arrive from
positive logic sources.
3.17 Use three NOR gates (nothing else) to implement the function Y(H} below ex-
actly as written. Assume the inputs arrive as follow: A(H), B(H\ C(H), D(L),
and £(L).
Y(H) = [(AD) -( B + C + £)](//)
3.18 Use three NAND gates (nothing else) to implement the function Z(H) below ex-
actly as written. Assume the inputs arrive as follow: A(H\ B(H), C(H), D(L), and
Z(H) - [(A + D) + (BCE)](H)
3.19 Name the gates used in each of the logic circuits shown in Fig. P3.3 and give the
mixed logic expression at each node in mixed logic notation. Use Figs. 3.20, 3.23,
and 3.24 as a guide if needed.
3.20 The CMOS circuits in Fig. P3.4 perform specific logic functions. Construct the physi-
cal and mixed logic truth tables for each circuit, indicate what logic function it performs
and give its two conjugate logic circuit symbols. Note that B is the inverse voltage
ofB .
3.21 Use two NOR gates and one XOR gate (nothing else) to implement the function Y(H)
below exactly as written. Assume the inputs arrive as A(H), B(H\ C(//), D(L),
and E(L).
Y(H} = [(A®D)-(B + C + £)](#)
3.22 Use three NAND gates, one EQV gate, and one inverter (nothing else) to implement
the function G(H) below exactly as written. Assume the inputs all arrive from positive