Page 290 - Engineering Digital Design

6.5 CODE CONVERTERS 261

Algorithm 6.2 Binary-to-BCD Conversion by the (x2)/(4-3) Process
(1) Shift the binary number to the left by one bit into the new LSD position.
(2) Add 001 1 to the new LSD iff the new LSD number is greater than 4 (0100), After
adding 3, shift left immediately.
(3) Repeat steps (1) and (2). When all binary bits have been shifted into digit positions,
the process ceases and the answer is in BCD.

To design converters by either Algorithm 6.1 or 6.2, it is not necessary to resort to
arithmetic means as implied by the algorithms. Rather, a modular approach is easily estab-
lished by constructing a relatively simple truth table followed by appropriate minimization
methods. The process is now illustrated by designing an 8-bit BCD-to-binary converter.

BCD-to-Binary Conversion A truth table matching BCD with the corresponding binary
from 0 to 19 is given in Fig. 6.20a. Inherent in this truth table is the shift-right/subtract-3
Algorithm 6.1. The decimal range 0 to 19 is chosen to illustrate the process but is easily
extended to 39, 79, or 99, etc. This truth table will be used to design a BCD-to-binary
module that can be cascaded to produce any size converter. It is possible to use a decimal
range of 0 to 99 for this purpose, but the size of the module is considered too large to be of
value for this example.
Shown in Fig. 6.20b are the K-maps and minimum cover for four of the five output
functions of the 2-digit BCD-to-binary module. The two-level minimum expressions for
the BCD-to-binary module, as read from the K-maps and truth table, are

B 4 = D 4D 2Di + D 4D 3
# 3 = D 4 D 3 Di + D 4 D 2 D] + D 4D 3
B 2 = D 4D 2Di + D 4D 2 + D 2D\ (6.17)
BI = D 4£>i + D 4 Di = D 4 © DI
BQ = DO by inspection,

which represent a gate/input tally of 1 1/27 excluding inverters but including one shared PI.
The logic circuit for this module is given in Fig. 6.21 a and is cascaded in Fig. 6.2 Ib to produce
the 8-bit BCD-to-binary converter. Notice that the four modules are cascaded in such a way
as to satisfy the right-shift requirement of Algorithm 6.1. If expansion beyond 8 bits is
needed, each additional bit requires that an additional module be added in cascade fashion.

BCD-to-Seven-Segment Display No discussion of code conversion is complete without
including the BCD-to-seven-segment decoder (converter). Light-emitting diodes (LEDs)
and liquid crystal displays (LCDs) are used extensively to produce the familiar Arabic
numerals. The use of the BCD-to-seven-segment decoder is an important means of accom-
plishing this.
Shown in Fig. 6.22a is the seven-segment display format and the ten decimal digits that
are produced by the decoder/display. The truth table for the converter is given in Fig. 6.22b
and features a blanking input BI, but lacks FDR since 0's are assigned to the six unused
input states.
The EV K-maps for the seven segment outputs are shown in Fig. 6.22c, where a
near-minimum POS cover for each has been looped out. This results in the following