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9.5 STUCK-AT FAULTS AND THE EFFECT OF HAZARD COVER 413

A(H)
B(H) J

C(H) 1
D(H) 1
1
N (H) ; LJ- u i
XOP
o ^^ f n
InP^C N xop(H)* J \ / T
Stuck-at 0 xup ^^ Fail, t \
* With hazard cover static -^
masking fault error 1-Hazards ^ rror
(a) (b)
FIGURE 9.20
Effect of stuck-at fault on function NXOP in Eq. (9.12). (a) AND representing the ABCD term and
showing a stuck-at fault on input C. (b) Timing diagram showing effect of the stuck-at 0 fault and the
masking effect of hazard cover.

two-level SOP or POS counterparts. This, of course, is one advantage in the use of XOP,
EOS, and CRMT circuits discussed in Chapter 5. However, if static hazards must be elimi-
nated in these circuits prior to fault testing, this advantage may be lessened or eliminated.
Static hazard cover must always be redundant cover (i.e., not essential to function represen-
tation). Redundant cover can make stuck-at fault testing more difficult and may even mask
an existing stuck-at fault. When considering the testability of a circuit, the designer must
consider the effect of any static hazard cover needed.
As an example, consider function NXOP in Eqs. (9.10) and (9.12) before and after the
addition of static hazard cover. Suppose there is a stuck-at-0 fault at any input to the term
ABCD. This fault causes an output error on the input condition 1011. However, the addition
of hazard cover ACD holds the output active and masks the presence of this fault. Thus, after
hazard cover is added, one cannot test for this fault by the standard methods of observing the
final output. The timing diagram in Fig. 9.20 illustrates the masking effect of hazard cover
in the NXOP function. This timing diagram can be easily understood if it is recalled that an
odd number of 1 's in an XOR string such as that for function NXOP in Eqs. (9.10) and (9.12)
yields a logic 1 for that function. Consequently, introducing the change 1111 —> 1011 into
these equations with and without the hazard cover ACD and with C = 0 results in the timing
diagram shown in Fig. 9.20b. In conclusion it can be stated that fault detection and location
test sets should be used prior to the addition of hazard cover; if not, some stuck-at faults
may not be detected and located.

FURTHER READING

The subject of static hazards in two-level combinational logic circuits is covered adequately
in texts by Breuer and Friedman, Katz, McCluskey, Tinder, Wakerly, and Yarbrough. Dy-
namic hazards and function hazards are also covered by McCluskey. However, there is no