Page 579 - Engineering Digital Design

FURTHER READING 549

designed on chip to be manufactured by the millions, an optimum design may be necessary
(hardware-wise and/or speed-wise), but with or without a minimum number of states.

FURTHER READING

Few texts cover the subject of output race glitches (ORGs). The known sources on this
subject are the texts of Fletcher, Shaw, and Tinder, and of these the last is by far the most
comprehensive. It is equally difficult to find further reading on the subject of static hazards
in the outputs of synchronous FSMs. The reason for this is not exactly clear. Again the best
source appears to be the text by Tinder.

[1] W. I. Fletcher, An Engineering Approach to Digital Design. Prentice Hall, Englewood Cliffs,
NJ, 1980.
[2] A. W. Shaw, Logic Circuit Design. Sanders College Publishing, Fort Worth, TX, 1993.
[3] R. F. Tinder, Digital Engineering Design: A Modern Approach. Prentice Hall, Englewood Cliffs,
NJ, 1991.

The subjects of asynchronous inputs, synchronizers and their failure, and metastability
appear to be covered to one extent or another by most texts in the field and in many journal
articles. Perhaps the best coverage for further reading on these subjects is found in the
text by Wakerly, with others by Fletcher, Tinder (both previously cited), Daniels, Katz,
McCluskey, and Unger all being a distant second choice.
The texts of Wakerly and Daniels cover the subject of mean time between failure (MTBF)
of synchronizer flip-flops and are recommended for further reading on this subject.

[4] J. D. Daniels, Digital Design from Zero to One. John Wiley & Sons, New York, 1996.
[5] R. H. Katz, Contemporary Logic Design. Benjamin/Cummings Publishing, Redwood City, CA,
1994.
[6] E. J. McCluskey, Logic Design Principles. Prentice Hall, Englewood Cliffs, NJ, 1986.
[7] S. H. Unger, The Essence of Logic Circuits. Prentice Hall, Englewood Cliffs, NJ, 1989.
[8] J. F. Wakerly, Digital Design Principles and Practices, 2nd. ed. Prentice-Hall, Englewood Cliffs,
NJ, 1994.

Of the journal articles on metastability and the synchronizer, none are more important
than those by Chaney, who has over many years established himself as a leading authority
on the metastability problem in synchronizers. In Chaney's article will be found measured
data on the MTBF of a variety of common flip-flops. Also, there are the earlier works of
Chaney et al., Stoll, and Veedrick that are worth reading for a more complete grasp of the
synchronizer problem. The advanced reader may find the theoretical work of Kleeman and
Cantoni more contributive to an understanding of the problem.

[9] T. J. Chaney, "Measured Flip-Flop Responses to Marginal Triggering," IEEE Trans. Comput.
C-32(12), 1207-1209 (1983).
[10] T. J. Chaney, S. M. Ornstein, and W. M. Littleneld, "Beware the Synchronizer," Dig. COMPCON,
San Francisco, Sept. 1972, pp. 317-319.
[11] L. Kleeman and A. Cantoni, "On the Unavoidability of Metastable Behavior in Digital Systems,"
IEEE Trans, on Comput. C-36(l), 109-112 (1987).