Page 580 - Engineering Digital Design

550 CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS

[12] P. A. Stoll, "How to Avoid Synchronization Problems," VLSI Design, Nov.-Dec., pp. 56-59
(1982).
[13] H. J. M. Veedrick, "The Behavior of Flip-Flops Used as Synchronizers and Prediction of their
Failure Rate," IEEE Journal of Solid State Circuits SC-15(2), 169-176 (1980).

Adequate treatments of clock skew are found in the texts of Fletcher, McCluskey,
Tinder, and Wakerly, all previously cited. Excellent coverage of clock generating circuitry
is provided in the text by Fletcher. Discussions on clock signal specifications, buffering,
and gating can be found in the text by Wakerly. For the advanced reader needing infor-
mation on the techniques for generating high-frequency clock waveforms from frequency
synthesizers, the texts by Best, Egan, and Rhode are recommended.

[14] R. G. Best, Phase-Locked Loops — Theory, Design and Applications. McGraw-Hill, New York,
1984.
[15] W. F. Egan, Frequency Synthesis by Phase Lock. Wiley Interscience, New York, 1981.
[16] U. L. Rhode, Digital PLL Frequency Synthesizers Theory and Design. Prentice Hall, Englewood
Cliffs, NJ, 1983.

Further reading on the subject of initialization (sanity) circuits is best found in the text
by Langdon and that by Tinder (previously cited). On the subject of debouncing circuits
the texts by Langdon, Tinder, and Wakerly are recommended, although the subject is to
one degree or another covered in other texts such as those by Daniels, Katz, and Unger, all
previously cited.

[17] B. G. Langdon, Jr., Computer Design. Computeach Press, Inc., San Jose, CA, 1982.

References covering the uses of ASMs, state tables, and state assignment rules in state
machine design are numerous. Good examples of all three of these subjects are found in
the texts by Hayes, Nelson et al., Roth, Wakerly (previously cited), and Yarbrough. The
text by Comer uses a unique graphical representation of sequential machines that appears
to draw from a combination of ASM chart notation and state diagram notation. Of the
journal articles on optimal state assignments, that by De Micheli et al. is perhaps the most
authoritative available.

[18] D. J. Comer, Digital Logic and State Machine Design, 3rd ed. Saunders College Publishing, Fort
Worth, TX, 1995.
[19] G. De Micheli, R. Brayton, and A. Sangiovanni-Vincentelli, "Optimal State Assignment for
Finite State Machines," IEEE Trans, on CAD/ICAS CAD-4(3), 269-284 (1985).
[20] J. P. Hayes, Introduction to Digital Design. Addison-Wesley, Reading, MA, 1993.
[21] V. P. Nelson, H. T. Nagle, B. D. Carroll, and J. D. Irwin, Digital Logic Circuit Analysis and
Design. Prentice Hall, Englewood Cliffs, NJ, 1995.
[22] C. H. Roth, Fundamentals of Logic Design, 4th ed. West, St. Paul, MN, 1992.
[23] J. M. Yarbrough, Digital Logic Applications and Design, West, Minneapolis/St. Paul, MN,
1997.

The formal approach to state reduction is nicely covered by numerous texts, includ-
ing those of Hayes, Katz, McCluskey, Nelson et al., and Yarbrough, all previously cited.