Page 630 - Engineering Digital Design

600 CHAPTER 12/MODULE AND BIT-SLICE DEVICES

Eq. (12.10),

D A = (ABC) 0 C 0 D = D @ (AB + C),

in literal form, which can be proved by applying the laws of XOR algebra in Section 3.11.
A cursory inspection of Eq. (12.12) and Table 12.1 indicates that the maximum number
of XOR operations is three, independent of ALFSR counter size, but only after simplifying
by application of Eqs. (3.25) and (3.13). Fortunately, three XOR operations can be handled
very easily by a standard four-input, even-parity generator module such as that in Fig. 6.32c.
The problem is, of course, in dealing with the large number of ANDed complements present
in the correction functions. If CMOS logic is permitted, the multiple input NOR gate in
Figure 8.46 can be used to great advantage. It has no fan-in limitations.
Table 12.1 and Eq. (12.12) apply to right-shifted ALFSR counters that sequence through
all 2" pseudo-random states and that are initialized into the all-zero state. Table 12.1 and
Eq. (12.12) can also be applied to left-shifted ALFSR counters if the Qj outputs are in-
terpreted in "reverse" fashion such that <2o is the MSB and Q n-\ the LSB. The corrected
Q n-2 • Qn-\) © f(Q') by omitting <2o,
feedback function now becomes (Q\ • Q 2
where /(Q') is the feedback function in Table 12.1 interpreted in reverse order. For example,
<2o © Qi ® Qi © Q4 = A 0 C © D 0 E for n = 8 .

12.5 ASYNCHRONOUS (RIPPLE) COUNTERS

All counters discussed in Sections 12.3 and 12.4 are classified as synchronous counters
because the flip-flops, of which the counters are constructed, are all triggered simultaneously
or very nearly so. Counters composed of T flip-flops that are triggered in series are called
ripple counters. Each T flip-flop is triggered off of the output from the next LSB flip-flop.
For this reason, they are classified as asynchronous counters even though the LSB flip-flop
is triggered by the external CK signal.
Shown in Fig. 12.38a is a general divide-by-2" ripple counter composed of toggle modules
of the type shown in Fig. 12.12c, a toggle module being nothing more than a divide-by-2
counter. Notice that the Q(H) output of each toggle module is the input to the FET clock
of the next MSB stage. In Fig. 12.38b is the timing diagram for the three LSB stages of
this ripple counter. The count, taken from outputs Q n-\ • • • QiQ\ <2o is shown to be in
ascending binary, an up-count, and that frequency is divided beginning with f CK + 2 for
<2o and ending with /CK -+- 2" for Q n-\. A sanity input permits the counter to be initialized
into the 0 • • • 000 state.
The direction of the count (Dn = 1 for down count and Dn = 0 for up count) of any
ripple counter can be altered by making any odd number of changes in the expression
Dn = RET © Q CK 0 QOUT- (12.13)

In this equation, RET = 1 for RET flip-flops or RET = 0 for FET flip-flops, Q CK = 1 if
triggering is from Q(H) of the next LSB stage or Q CK — 0 if triggering is from Q(L), and
QOUT = 1 if the count is read from Q(H) or QOUT = 0 if read from Q(L). Thus, any odd
number of changes (parameters or operators) in Eq. (12.13) changes the count direction.
For example, if RET toggle modules are used in Fig. 12.38a, a down-count occurs. Thus,