Page 751 - Engineering Digital Design

14.10 DETECTION AND ELIMINATION OF TIMING DEFECTS 717

1 . A delay Ar D placed on the initiator B input to the first invariant JQ causes a critical race
to the race gate between the initiator B and the second invariant y\. If At D exceeds
the minimum path delay requirements, y\ wins the race and the d-trio will be formed.
If A? D is not of sufficient magnitude, the initiator input B wins the race and no d-trio
will form. Should the d-trio be formed, an output Z will be issued for a duration equal
to the difference between At D and the minimum path delay requirements for d-trio
formation.
2. An ANDing race (ROD) is indicated by the term y \ B in y$, as indicated in Eqs. (14.21).
No ORing RG is possible according to Figs. 14.27a and 14.28a.
3. The indirect path (IPo) must not be inconsistent with A,yi,yoinY\ and must contain
either B or B in Y\ . Therefore, the I?D is by way of the term y$B \nY\.
4. Based on this information and with reference to Fig. 14.29, the theoretical minimum
path delay requirement for d-trio formation is given by the inequality

(Ar D ) > (n +T 4 + rio) = (TINV + 2r p), (14.23)
where, as previously, T P is the path delay through a gate (e.g., a two- or three-
input NAND gate), and TJ^V = r is the path delay through an inverter. Accordingly,
Eq. (14.23) does not take into account the gate path delay dependence on fan-in.

The corrective action required to prevent the E-hazard or d-trio from forming, is indicated
in Fig. 14.29 by a counteracting delay in the feedback path of the second-invariant state
variable y\. Thus, the theoretical corrective action required to eliminate these defects is
given by the inequalities

2r p + &t Correct) (14.24)

and

(T INV + 2T P + &t Comct). (14.25)

Notice that if A/correc/ = Af£, the inequalities of Eqs. (14. 24) and (14. 25) are easily satisfied.
Also, observe that the delay Ar £ is effective in causing the E-hazard to form at any point
along the path E to F (see the large nodes in Fig. 14.29), including the intervening two-input
NAND gate. This is characteristic of any ORing race gate, a feature not shared with the
ANDing race gate.
Further verification of the results presented so far is provided by the timing diagrams in
Fig. 14.30. Presented in Fig. 14.30a is the result of E-hazard formation indicating an error
transition 11 -» 01 — >• 00 due to a delay Af £ = 5r p positioned anywhere along the path
between large nodes E and F (including the intervening NAND gate) shown in Fig. 14.29.
Recall that under the input change AB — »• AB from state 11 the correct transition should
be 1 1 -> 01, but because of the unwanted path delay A.t E an error transition is forced to
occur. A path delay of At E = 5r p clearly exceeds the minimum path delay requirements
for E-hazard formation given by Eq. (14.22).
The formation of the d-trio is illustrated by the timing diagram in Fig. 14.30b. Here, a de-
lay of A?£> = 5T P, positioned as shown in Fig. 14.29, causes an error pulse in state variable
jo and output Z of duration 5r p — (TINV + 2r p) = 3r p — TINV- The d-trio has the appearance