Page 453 - Mathematical Techniques of Fractional Order Systems
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438  Mathematical Techniques of Fractional Order Systems


            generating function is defined as (Barbosa and Machado, 2006; Vinagre
            et al., 2003):
                                                      6 α
                                                  21
                                   21  6 α   2 12z
                                ðwðz ÞÞ  5             ;             ð14:74Þ
                                             T 11z 21
            where T is the sampling time and 0 , α , 1. The expression in the right hand
            side of Eq. (14.74) can be evaluated either by power series expansion (PSE) or
            continued fraction expansion (CFE). Shah et al. (2017) utilized the latter
            method due to the fact that the CFE has wider range on convergence than PSE.
            For example, the Arneodo system was implemented using the set of equations:
                                      21
                                  N x ðz Þ
                                         xðkÞ 5 yðk 2 1Þ;            ð14:75aÞ
                                      21
                                  D x ðz Þ
                                      21
                                  N y ðz Þ
                                         yðkÞ 5 zðk 2 1Þ;           ð14:75bÞ
                                      21
                                  D y ðz Þ
                     21
                  N z ðz Þ                                  3
                        zðkÞ 52 β xðkÞ 2 β yðkÞ 2 β zðk 2 1Þ 1 β x ðkÞ;  ð14:75cÞ
                     21         1       2      3          4
                 D z ðz Þ
            where N x , D x , N y , D y , N z , and D z are the polynomials of the CFE approxima-
            tion. The system exhibits chaotic behavior with the parameters: β 52 5:5,
                                                                   1
            β 5 3:5, β 5 0:8, β 52 1:0, and commensurate order α . 0:86. The
                               4
                      3
             2
            implementation is made on DE2-115 board that utilizes a Cyclone IV
            (EP4CE115F29C7N) FPGA chip. The state variables are represented by 32-
            bits fixed point representation. This implementation utilized: 57% of the
            available (300) 9-bit multipliers, 5% of the available combinational func-
            tions, and only 1% of the available logic registers. The MLE of the generated
            Arneodo system was calculated to be 0.2614.
            14.8.2 Grunwald Letnikov Based FPGA
                       ¨
            Implementation of FOCS
            In order to implement Eq. (14.8a c) on FPGA, only a limited number of
            past values of the variables can be used. However, as the size of this window
            approaches N, the solution gets closer to the exact according to the short
            memory principle (Podlubny, 1998). Based on this assumptions, the frac-
            tional order multiscroll attractor can be simulated by (Tolba et al., 2017):
                                                  L
                                                 X
                            5 xðt k21 Þ 2 yðt k21 ÞÞh 2  w ðq 1 Þ xðt k2j Þ;
                                             q 1
                                                      j
                          x t k  ð                                   ð14:76aÞ
                                                  j51
                                                            L
                                                           X
                   5 signðxðt k21 ÞÞ½1 2 mzðt k21 Þ 1 Gðzðt k21 ÞފÞh 2  w ðq 2 Þ yðt k2j Þ;
                                                       q 2
                                                               j
                 y t k  ð
                                                           j51
                                                                    ð14:76bÞ
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