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2/44 Electrical and electronics principles
      The first example shows that the parentheses may be removed   numbers as the standard series, but have ‘LS’ inserted before
      by multiplying out, as in normal  arithmetic.  The second  two   the type code (e.g. SN74LS00). The operating speed is about
      examples have no arithmetic counterpart.       twice as high and the power consumption is about 20% of  the
        De Morgan’s theorem states that, in any logical expression,   standard series. Schottky devices are, however, slightly more
      AND can  be replaced  by  OR and vice versa,  provided  that   expensive.
      each term is also replaced  with its inverse  complement.  The
      resulting  expression is then the inverse of  the original.   2.3.20.2  CMOS
      Example 1                                      The problematic features of  the power supply associated with
      From ABC we negate to                          the TTL family of  logic devices has been  largely responsible
      ABC =  + B + c                                 for the growth of its major competitor, CMOS. CMOS ICs are
                                                     based on the field effect transistor and can operate off a range
      Hence                                          of  power  supply  voltages  between  k3 V  to  +18 V.  CMOS
      ABC  = X+B +C                                  devices  dissipate  very  little  power,  are  very  cheap  and  are
                                                     simple in operation. The fan out is about 50 and they have a
      Example 2                                      far greater immunity to power supply noise. The noise immun-
      From F  = AB + CD we negate to                 ity of  CMOS devices means  that there is no requirement  for
      F  = (2 + B) + (C + a)                         smoothing  capacitors  to  the  extent  that  they  are  generally
                                                     found in TTL circuitry.
      Applying  De Morgan again,                       There are also some disadvantages associated  with CMOS
      F  = (2 + B).(C + a)                           devices, the main one being that CMOS is slower than TTL,
                                                     roughly about one tenth of the equivalent TTL circuit. CMOS
      The equivalence of the original and the final expressions in the   ICs are also very sensitive to electrostatic voltages. Manufac-
      above two examples may be checked by using a truth table.   turers  do  build  in  some  safety  features  to  reduce  the  elec-
                                                     trostatic  sensitivity,  but  CMOS devices must still be handled
                                                     with  due  care. Table 2.4  gives a  brief  comparison  between
      2.3.20  Digital electronic gates               TTL and CMOS devices.
      The principles of  Boolean algebra have been considered with
       respect  to  manually  switched  circuits.  In  modern  digital   Table 2.4  Comparison between TTL and CMOS devices
       systems the switches are formed with transistors for speed of
       operation, and they are generally referred  to as ‘gates’. Over   Property   TTL   CMOS
       the  years,  various  technologies  have  been  developed  in  the
       manufacture  of  logic gates. The earliest  forms of  electronic   Power supply   5 V k 0.25 V   3 V to 18 V d.c.
       gate were based on the unidirectional conduction properties of   Current required   Milliamps   Microamps
       diodes.  Diode  logic  gates  have  now  been  superseded  by   Input impedance   Low   Very high
       transistor-transistor  logic  gates  (TTL)  or  the  more  recent   Switching speed   Fast - 10 ns   Slow - 300 ns
       CMOS family of  logic gates.                  Fan out        10             50
        The  internal  construction  and  operation  of  modern  logic
       gates may be quite complex, but this is of  little interest to the
       digital systems designer. Generally, all that the designer need
       to know is the power supply voltages, the transient  switching   2.3.21  Gate symbols
       times, the  ‘fan out’ and  the  ‘fan in’.  Fan  out  refers  to  the   Having  defined  a  system  output  in  terms  of  a  Boolean
       number of  similar gates which can be driven from the output   expression,  the  actual  circuit  can  be  constructed  using  the
       of  one gate. Fan in, on the other hand, denotes the number of   required  gates  selected  from  the  logic family  chosen.  Gen-
       similar gate outputs which can be safely connected to the input   erally,  the  design  will  be  centred  round  the  more  readily
       of  one gate.                                 available  NAND  and NOR logic gates.  In laying out  a gate
                                                     interconnection  diagram, standard symbols are used to repre-
       2.3.20.1  TTL                                 sent  the  individual  gates.  Unfortunately,  no  universal  set of
                                                     symbols has emerged, and several systems are in current use.
       The TTL family is based  on the  bipolar  junction  transistor,   Figure  2.90  summarizes  the  most  common  gate  symbol
       and was the first commonly available series of  logic elements.   systems.
       TTL logic gates are rapid-switching devices (the SN7400, for
       example,  takes  just  15 ns  to  change  state).  The  standard
       power  supply is 5 V with  a  low tolerance  band  of  f0.25 V.   2.3.22  Logic systems using simple gates
       This, in turn, necessitates  a reliable power supply regulation
       which  is  reasonably  facilitated  through  the  great  variety  of   A  vending machine which dispenses either tea  or coffee can
       supply regulators which are now available in IC form. For the   serve  as  an  illustrative  example.  The  logic  circuit  may  be
       SN74 series TTL ICs. the fan out is about 10.   realized  using AND gates as shown in Figure 2.91.
        A  TTL-based  system  can  draw  quite  large  instantaneous   The money input is common to both gates, and the system,
       loads  on  a  power  supply,  and  this  can  result  in  substantial   although workable,  has, a minor fault in that if  both buttons
       interference  ‘spikes‘ in the power lines. Since the spikes can   are  pressed,  after  the  money  criterion  is  satisfied, then  the
       upset the normal operation of the system it is common practice   output will be both tea and coffee. This fault can be designed
       to connect small capacitors directly across the power lines, as   out  of  the system by  extending the logic circuit  as shown in
       close to the  TTL ICs as possible.  One capacitor,  0.1-10  pF,   Figure 2.92.
       per five ICs is sufficient in most instances.   The extended system  incorporates  a  NAND  gate  and  an
        TTL circuits  are  continually  being  improved  and  a  major   additional  AND gate. If  both  buttons  are now pressed  then
       recent  advance  has been  the  introduction  of  the low-power   the output from G3 will be 0. With the output 1 from GI, the
       ‘Schottky’  TTL  circuits.  These  use  the  same  generic  code   output from G4 will be 0 and the machine will dispense tea. On
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