Page 250 - Mechanical Engineers' Handbook (Volume 2)
P. 250

Mechanical Engineers’ Handbook: Instrumentation, Systems, Controls, and MEMS, Volume 2, Third Edition.



                                                                                    Edited by Myer Kutz




                                                                   Copyright   2006 by John Wiley & Sons, Inc.





                           CHAPTER 8
                           DIGITAL INTEGRATED CIRCUITS:
                           A PRACTICAL APPLICATION
                           Todd Rhoad
                           Austin, Texas
                           Keith Folken
                           Peoria, Illinois
                           1  REDUCTION OF PROCESSOR             7   LOGIC GATES                246
                              LOAD                        239
                                                                 8   COUNTERS                   247
                           2  FIELD-PROGRAMMABLE
                              GATE ARRAYS                 240    9   ADDERS, REGISTERS, AND
                                                                     MULTIPLEXERS               249
                           3  LOGIC BLOCKS                241
                                                                 10  MEMORIES                   249
                           4  LOOKUP TABLES               242
                                                                 11  PROGRAMMABLE I/O
                           5  FLIP-FLOPS                  243        BLOCKS                     251
                              5.1  D Flip-Flops           244
                              5.2  R–S Flip-Flops         244    12  PROGRAMMABLE
                              5.3  T Flip-Flops           245        INTERCONNECTS              251
                              5.4  J–K Flip-Flops         246
                                                                     REFERENCES                 253
                           6  BOOLEAN LOGIC NOTATION      246




            1   REDUCTION OF PROCESSOR LOAD

                           Today’s processors can make many calculations in a very short amount of time. Embedded
                           controllers make many repeated calculations several times a second. In many embedded
                           controllers, such as an engine control or plant process control, the processor takes several
                           inputs from outside sources, does some computation with those values, and then takes some
                           action. This may be in the form of an output to the system, an alarm, or just a log of the
                           data. The processor’s mathematical calculations can be very time intensive. If accuracy is
                           required, these calculations must done using several digits, sometimes with floating-point
                           numbers. To take some of this load off of the processor, a field programmable gate array
                           (FPGA) may be used.
                              An FPGA is a device of logic gates. These logic gates can be used to take the place of
                           the computationally intensive mathematical operations that the processor would normally
                           perform. For example, a process controller is asked to measure 10 analog inputs every 200
                           ms. The controller must compute a running average of the last three samples of each input.
                           Using this average, several multiplication and division computations are made. To offload
                           the processor, an FPGA could be used to make these repetitive calculations and feed the
                           results back to the processor.


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