Page 252 - Mechanical Engineers' Handbook (Volume 2)

3 Logic Blocks 241

are built using static random-access memory (SRAM) technology, similar to microprocessors.
The other common process technology is called antifuse, which has benefits for more plen-
tiful programmable interconnect.
Reprogrammable FPGA technologies tend to be SRAM based. The routing matrices are
usually implemented using pass gates driven by the value of the SRAM memory cell assigned
to it. Lookup table (LUT) function generators are used to program the function of the logic
block. These LUTs are small SRAM cells that have four or five inputs, which are the address
lines of the SRAM cell. The output of the SRAM cell is the output of the function generator.
The programmable FF after the logic block is programmed using pass gates. Then, to pro-
gram the function of the logic block, the contents of the SRAM cell are loaded and configure
the block to be either registered or combinatorial. Without any sort of external memory,
SRAM-based FPGAs will lose their configuration if the device is turned off. Therefore,
erasable programmable read-only memory (EPROM), or flash memory, connected serial or
parallel, is used to provide the configuration to the FPGA during startup. That is, this con-
figuration memory holds the program that defines how each of the logic blocks functions,
which I/O blocks are inputs and outputs, and how the blocks are interconnected together.
There are a few advantages and disadvantages in using FPGA-assisted designs. Pipelin-
ing is a hardware technique of segmenting a complex operation into stages so that multiple
computations can be performed simultaneously. Pipelining is a natural choice due to the
discrete and regular quantities of FPGA logic blocks. Memory located at the end of the logic
blocks completes the design and uses the storage as pipeline stage registers. The biggest
feature of FPGA pipelining is the ability to combine numerous complex computations into
a single pipeline. FPGAs have the ability to chain together any sequence of operations as
required by the algorithm. Such deep pipelines are difficult to abstract for general-purpose
CPUs; therefore, FPGAs offer computational potential found elsewhere only in ASICs
(application-specific integrated circuits). Another major advantage is the ability to implement
a large degree of computational parallelism. The parallelism most concerned here is data
and algorithmic parallelism. Data parallelism is the ability to regularly process a large data
set concurrently. Algorithmic parallelism refers to the ability to operate multiple independent
algorithms at the same time. A combination of these two types can result in high-throughput
devices with low-speed parts, which is simply streaming high-speed data through an array
of low-speed computational units. FPGAs can also minimize computational logic and delay
by utilizing partial evaluation techniques to reduce multivariable functions to less compli-
cated functions based on information provided at compilation.
FPGAs do suffer physical constraints in that they are slower and are degraded in density,
when compared to ASICs, due to the use of configurable SRAM-based devices to implement
gates and interconnections. Gate density is extremely important since the size of the gate
array determines how much logic can be implemented. Aside from physical constraints,
FPGAs require relatively long delays for reprogramming the device. Current chips require
configurations to be downloaded one at a time, resulting in significant dead time on the order
of a few milliseconds. For applications where the process time is of the same order, signif-
icant issues can arise. Other weaknesses for FPGA-based designs include poor floating-point
performance, poor data proximity, and overall design complexity.

3 LOGIC BLOCKS
The logic block of an FPGA is the core building block and is used to implement combi-
national and sequential logic. This block implements the actual logic functions for config-
urable computing. A general representation of a logic block is shown in Fig. 2. This model