Page 102 - Mechatronic Systems Modelling and Simulation with HDLs

5.4 CO-SIMULATION BY SOFTWARE COMPILATION 91

to the timing of the return of the software, the question is raised as to whether
the sequence of load or store instructions includes reference to the I/O ports, i.e.
whether it wants to exchange data from within itself with the hardware. If this is the
case then the processing of the software is interrupted immediately. Otherwise the
software runs until the predefined time point. Upon return, the C routine informs
the hardware of the time point t that it reached. Since the software has run in zero
time from the point of view of the hardware, the hardware should now be simulated
up to time point t so that time equality exists between software and hardware, and
thus data can be exchanged if necessary. However, the sequence described up until
now only functions as long as no interrupt is triggered. In the event of an interrupt
occurring, the state of the software is initially brought to the time point at which
the interrupt occurred. Then synchronisation occurs and the programme counter
is set to the interrupt vector, whereupon the normal sequence can once again be
resumed. The forms of synchronisation described thus far will be considered in
more detail in what follows.

Synchronisation without interrupt

Let us initially assume that no access to I/O ports has occurred during the process-
ing of the software, see Figure 5.4. Before the software can once again proceed
for a certain period of time, a synchronisation must take place. This means primar-
ily that we wait until the hardware has also been simulated up to the time point
at which the software currently stands. When the software and hardware show
the same value for time, the software can once again proceed and the described
procedure runs from the start.
Figure 5.5 illustrates the case of access to the I/O port. Here the occurrence
of a corresponding load or store command leads to the software sequence being

Synchronisation Synchronisation

Hardware simulation Hardware simulation

Hardware
Software Software Time
simulation

Software
simulation jsr adq ..................

Predetermined time
clra bra .................. passed

Figure 5.4 Synchronisation between hardware and software after the time allotted for the
software has elapsed