Page 99 - Mechatronic Systems Modelling and Simulation with HDLs

88 5 SOFTWARE IN HARDWARE DESCRIPTION LANGUAGES

WHEN op_sub =>=> -- Perform
reg(r3) := reg(r1) - reg(r2); -- subtraction
zflag := (reg(r3) = 0) ? ‘1’ : ‘0’; -- Zero flag?
...
...
WHEN op_and => -- Perform
reg(r3) := reg(r1) and reg(r2); -- logical AND
zflag := (reg(r3) = 0) ? ‘1’ : ‘0’; -- Zero flag?
...
...
WHEN op_load => -- Load reg.
disp := mem(pc); -- Determine disp.
pc := pc + 1; -- Increment PC
adr := To_Nat(reg(r1) + disp); -- Determine address
reg(r3) := mem(adr); -- Load
...
WHEN op_store => -- Save reg.
disp := mem(pc); -- Determine disp.
pc := pc + 1; -- Increment PC
adr := To_Nat(reg(r1) + disp); -- Determine address
mem(adr) := reg(r3); -- Store in mem.
...
WHEN op_branch_on_zero => -- Jump command
IF (zflag = ‘1’) THEN -- If flag = 1
disp := mem(pc); -- Determine disp.
pc := pc + 1; -- Increment PC
adr := pc + To_Nat(disp); -- Determine address
pc := adr; -- Set PC
...
END IF;
...
WHEN others =>
-- Unknown opcode ...
ASSERT false REPORT "illegal instruction"
SEVERITY warning;
WAIT;
END CASE;
END PROCESS;
END ARCHITECTURE;

Hardware description 5.1 VHDL description of a simple processor as software interpreter

5.4 Co-simulation by Software Compilation

5.4.1 Introduction
The approach described in the previous section interprets software during the run-
ning time in order to process it. This generates a considerable cost to be paid