Page 98 - Mechatronic Systems Modelling and Simulation with HDLs

5.3 CO-SIMULATION BY SOFTWARE INTERPRETATION 87

the Opcode is separated, and the addresses of the operands evaluated. There
then follows a large CASE instruction, which serves to decode the operation in
question. A few instructions are provided for each opcode, which may perform
arithmetic or logical actions, set the PC in the event of jumps, calculate flags and
much more.

ARCHITECTURE interpreter OF cpu IS
-- Type declaration for register and main memory ...
TYPE registers IS ARRAY (0 TO 31) OF
std_logic_vector(31 downto 0);
TYPE memory IS ARRAY (0 TO 512) OF
std_logic_vector(31 downto 0);
BEGIN
cycle: PROCESS
VARIABLE reg : registers; -- Registers
VARIABLE mem : memory; -- Memory
VARIABLE pc : natural; -- Programme counter
VARIABLE adr : natural; -- Address variable
VARIABLE inst : std_logic_vector -- Instruction
(31 downto 0);
VARIABLE disp : std_logic_vector -- Displacement
(31 downto 0);
VARIABLE opcode : std_logic_vector -- Opcode
( 7 downto 0);
VARIABLE r3, r1, r2: natural; -- Register adr.
VARIABLE i8 : integer; -- 8 bit number
VARIABLE zflag : std_logic; -- Zero flag
...
BEGIN
...
inst := mem(pc); -- Fetch instruction
pc := pc + 1; -- Increment PC
opcode := inst(31 downto 24); -- Extract opcode
r3 := To_Nat(inst(23 downto 16)); -- Determine
r1 := To_Nat(inst(15 downto 8)); -- register adr.
r2 := To_Nat(inst( 7 downto 0));-- from instruct.
i8 := To_Int(inst( 7 downto 0)); -- Immediate Op.
- Decode opcode ...
CASE opcode IS
WHEN op_add => -- Perform
reg(r3) := reg(r1) + reg(r2); -- addition
zflag := (reg(r3) = 0) ? ‘1’ : ‘0’; -- Zero flag?
...
WHEN op_add_immediate => -- Perform
reg(r3) := reg(r1) + i8; -- addition imm.
zflag := (reg(r3) = 0) ? ‘1’ : ‘0’; -- Zero flag?
...