Page 272 - A Practical Guide from Design Planning to Manufacturing
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Out
                                  V dd
               V dd
                              V ss
                                  V
                                  V
                              V
                              V
               V
               V
                       In
               V dd
                              V ss
                                  V dd
                              V
                              V
               V
               V
                                  V
                                  V
                                        PMOS  P  W p  W  W  p  Out  In  NMOS  Wn  V ss  V  V  V ss  V  V  3  Step  2  Step
                                         P+              N+
              PMOS  W p /L  W  W  W n /L  W  W  NMOS  L  P+  L  N+  1  Step
                                               N-Well          P-Well
                                   N+                     P+
                                    Well  tap              Well  tap  Inverter layout.
                       Out
               V dd  V  V  W p /L  W  W  W n /L  W  W  V ss  V  V
                                      N-well  P-well  P+  N+  Poly  Contact  M1  Figure 8-3
                       In                                   Palate




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