Page 349 - A Practical Guide from Design Planning to Manufacturing

Microprocessor Packaging 319

solder bumps (also called C4 bumps) are created across the face of the
die, and these bumps match pads connecting to the substrate intercon-
nect. Whereas wire-bond connections must be made one at a time, flip-
chip connections are made all at once as the die is pressed into the
package and heated to allow the solder bumps to reflow. Because the
solder bumps are placed across the entire face of the die, thousands of
connections can be made. The inductance and capacitance of these con-
nections is minimized since there are no flying lead wires connecting the
die to the substrate.
Although the electric connections made by flip-chip are superior, the
actual physical connection to the substrate is more of a problem. In a
wire-bond package, the backside of the die is glued to the substrate
before any lead connections are made. The die rests directly on the sub-
strate allowing for a good bond. In flip-chip packages, the die rests on
top of the solder bumps, which rest on the package substrate. If the CTE
of the die and the package are not well matched, then the solder bumps
alone will not be sufficient to hold the die on the package. As the die
heats up, stress could cause the solder bumps and die to tear free of the
package. To prevent this, the die must be glued to the package, but coat-
ing the package with glue before attaching the die will prevent good
electrical connections by the solder bumps. The common solution is to use
capillary underfill (CUF) materials.
After the die is placed facedown on the substrate and the solder bumps
are reflowed, a CUF epoxy is spread at the sides of the die in the gap
between the die face and the package. Through capillary action, the under-
fill material naturally flows between the C4 bumps and fills the gap
between the die and the package. After the epoxy has cured, it will hold
the die in place and protect the solder bumps from external contaminants.

Decoupling capacitors
Many packages include some passive components in addition to active
chips, and one commonly added component is decoupling capacitors, also
called decaps. As processor clock frequency and power have increased, pro-
viding a steady supply voltage to the processor has become increasingly
difficult. The amount of electrical current drawn by the processor can
change dramatically in just a few clock cycles as different parts of the
processor begin or finish calculations. Power-efficient designs work hard
to switch only those gates that are being used at that particular moment.
This reduces the average power of the processor but will increase the
maximum change in current that is possible from one cycle to the next.
Sudden increases in current cause the supply voltage to droop, which
slows the speed of the logic gates. Too large a droop and some circuit
paths on the die may not be able to operate properly at the processor