Page 50 - A Practical Guide from Design Planning to Manufacturing

26 Chapter One

Ideal scaling reduces all the vertical and horizontal dimensions by the
same amount. This keeps the capacitance per length constant but
greatly increases the resistance per length. In the end the reduction in
wire capacitance is offset by the increase in wire resistance, and the wire
delay remains constant. Scaling interconnects this way would mean
that as transistors grew faster, processor frequency would quickly
become limited by the interconnect delay.
To make interconnect delay scale with the transistor delay, constant-R
scaling can be used. By scaling the vertical and horizontal dimensions
of the wire less than its length, the total resistance of the wire is kept
constant. Because the capacitance is reduced at the same rate as ideal
scaling, the overall RC delay scales with the wire length. The downside
of constant-R scaling is that if S is also scaling the device dimensions,
then the area required for wires is not decreasing as quickly as the
device area. The size of a chip will be rapidly determined not by the
number of transistors but by the number of wires.
To allow for maximum scaling of die area while mitigating the increase
in wire resistance, most manufactures use quasi-ideal scaling. In this
scheme horizontal dimensions are scaled with wire length, but vertical
dimensions are scaled more slowly. The capacitance per length increases
only slightly and the increase in resistance is not as much as ideal scal-
ing. Overall the RC delay will decrease although not as much constant-R
scaling. The biggest disadvantage of quasi-ideal scaling is that it
increases the aspect ratio of the wires, the ratio of thickness to width.
This scaling has rapidly led to wires in modern processors that are twice
as tall as they are wide, but manufacturing wires with ever-greater
aspect ratios is difficult. To help in continuing to reduce interconnect
delays, manufactures have turned to new materials.
In 2000, some semiconductor manufacturers switched from using
aluminum wires, which had been used since the very first integrated cir-
cuits, to copper wires. The resistivity of copper is less than aluminum
providing lower resistance wires. Copper had not been used previously
because it diffuses very easily through silicon and silicon dioxide. Copper
atoms from the wires could quickly spread throughout a chip acting as
defects in the silicon and ruining the transistor behavior. To prevent this,
manufacturers coat all sides of the copper wires with materials that act
as diffusion barriers. This reduces the cross section of the wire that is
actually copper but prevents contamination.
Wire capacitances have been reduced through the use of low-K
dielectrics. Not only the dimensions of the wires determine wire capac-
itance but also by the permittivity or K value of the insulator sur-
rounding the wires. The best capacitance would be achieved if there were
simply air or vacuum between wires giving a K equal to 1, but of course
this would provide no physical support. Silicon dioxide is traditionally