Page 96 - Microsensors, MEMS and Smart Devices - Gardner Varadhan and Awadelkarim

MONOLITHIC PROCESSING 77

protective layer of oxide is regrown in an oxygen atmosphere. In practice, the diffusion
coefficient D does vary itself with the level of doping, increasing somewhat linearly with
arsenic and quadratically with phosphorus. As a result, calibrated charts, instead of a
simple mathematical formula, are used to determine the doping profiles.
In the second doping technique, namely, ion implantation, the dopant element is ionised,
accelerated to a kinetic energy of several hundred keV, and driven into the substrate. This
alternative method is discussed in Section 2.5.2.
After predeposition and drive-in steps, the oxide protection layer is stripped off using a
wet or dry etch to leave the n-regions defined in the p-type substrate. An n-type epi-layer
of 4 to 6 um in thickness is grown on top of the substrate (see Section 4.2.3) to create the
buried n-type areas within the p-type substrate. The buried n-layer is used to minimise
both the collector series resistance of the vertical n-p-n transistor that is formed later and
the common-base (CB) current gain, F, of the parasitic p-n-p transistor formed by the
collector and base of the lateral p-n-p transistor and the substrate. However, the buried
n-regions can diffuse further into the epi-layer at elevated temperatures, and so caution
is required in any subsequent processing.
The transistors need to be electrically separated from each other, and there are a number
of techniques with which to do this. Common techniques used are oxide isolation, based
on local oxide isolation of silicon (LOCOS), junction isolation (JI) based on a deep boron
dope, or trench isolation, which is useful for minimising parasitic capacitance. At this
stage, a second mask (mask 2) is used to define the regions into which boron is implanted
and thus isolate one transistor from another (see Figure 4.12).
+
Then the deep n -type contacts of the vertical n-p-n collector and lateral p-n-p base
are defined using a third mask in another patterning process, followed by an extrinsic
p-type implant for the base of the vertical n-p-n transistor and for both the emitter
and collector of the lateral p-n-p transistor (mask 3). The relatively thick, highly doped
extrinsic layer is followed by a thinner, lighter doped intrinsic base implant (mask 4)
below the emitter in the vertical n-p-n transistor. The lighter doping provides for a large
common-emitter (CE) current gain B F.
+
Next, the heavily doped n contact to the emitter in the vertical n-p-n transistor
is implanted (mask 5) to complete the transistor structures. Finally, the oxide layer is
patterned (mask 6) to form contact holes through to the transistor contacts and substrate,
and then the metal interconnect (normally 100 to 300 nm of aluminum) is deposited either
by physical evaporation or by sputtering and is patterned (mask 7) to form the completed
IC. Figure 4.13 shows the side view of two devices: the vertical n-p-n transistor and
lateral p-n-p transistor.
In some cases, a passivation layer of SiO2 or some other material is deposited and
patterned (mask 8) to serve as a physical and chemical protective barrier over the circuit.
This depends upon the proposed method of packaging of the die (see Section 4.4) and
the subsequent use. The complete bipolar process described here is summarised in
Figure 4.14.
It could be simplified by fabricating, for example, a pure n-p-n bipolar process, and, in
fact, most of the transistors in monolithic ICs are n-p-n structures. However, although the
characteristics of p-n-p transistors are generally inferior to an n-p-n transistor, as stated
in the preceding text, they are used as active devices in operational amplifiers, and as the
injector transistors in the IIL mentioned earlier. Similarly, a substrate p-n-p transistor