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Small-Signal Analysis of Cascaded Systems                     55


              such an approach, based on the Opposing Argument Criterion, fails
              when used with other less conservative criteria.)
                 More recent stability criteria include the Three-Step Impedance
              Criterion (T-SIC) [40], the Unified Impedance Criterion (UIC) [41],and
              the Maximum Peak Criteria (MPC) [42,43]. The T-SIC [40] relaxes the
              conservativeness of previous criteria because it does not assume that G S in
              (2.93) is necessarily a stable transfer function, which is typical of regulated
              source subsystem. For this reason, the impedance criterion should not be
              applied on the minor loop gain defined in (2.94), but rather on an
              extended minor loop gain defined in [40]. All previous stability criteria
              were developed for source subsystem interaction alone or load subsystem
              interaction alone by using the Middlebrook’s Extra Element Theorem
              (EET) [44]. Derived by using the 2EET [45], the UIC [41],particularly
              suitable for cascade connected subsystems, constructs the minor loop gain
              considering the simultaneous interaction of both source and load subsys-
              tems. The last proposed stability criterion in order of time is the MPC
              [42,43] which defines the minimum forbidden region for the minor loop
              gain among all prior stability criteria (Fig. 2.29). Such a forbidden region
              is determined by the maximum allowable peak of the sensitivity function,
              providing a direct measure of the stability robustness. However, as also
              demonstrated in [42,43], the state of the stability robustness strongly suffers
              from the interface where the minor loop gain is measured.



              2.6.1.1 Simulation Example
              As an illustrative example, an averaged model simulation of a cascade of a
              buck converter with a Voltage Source Inverter (VSI) in Fig. 2.30 is consid-
              ered. The values of voltages and components for both buck converter and
              VSI are also reported in Fig. 2.30. The controllers of both the buck converter
              and VSI are designed according to the procedure presented in Section 2.5.
                 The load VSI, modeled in synchronous dq coordinates [46], is con-
              trolled by an inner PI current mode (PICM subscript) loop with crossover
              frequency f c_PICM 5 1 kHz and phase margin PM_ PICM 5 80 degrees, and
              an outer PI voltage (PICM_FB subscript) loop with crossover frequency
              f c_PICM_FB 5 0.1 kHz and phase margin PM_ PICM_FB 5 80 degrees. Due
              to its importance in the small-signal stability analysis of the cascade system,
              Fig. 2.31 depicts how the input impedance of the VSI is modified by effect
              of the control action with respect to the open-loop (OL subscript) case.
              Notice that by the addition of the PI current loop and then of the outer PI
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