Page 382 - Op Amps Design, Applications, and Troubleshooting
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358 DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSION
The analog input signal provides one input to a voltage comparator. The sec-
ond input comes from the output of a D/A converter. The input to the D/A con-
verter is provided by an addressable latch called the successive approximation
register (SAR). Each bit of this register can be selectively set or cleared by the con-
trol unit. The control unit can be an internal portion of an integrated circuit, or it
may be a complete microprocessor system. In any case, the overall operation of
the successive approximation converter is described.
Let us suppose that the analog input voltage is 5.7 volts. Let us further sup-
pose that the SAR and D/A converters are 4-bit devices that provide 0,625 volts
per step at the output of the D/A converter. Finally, let us assume that the SAR is
initially set to 1000, thus producing a 5-volt output for the D/A converter.
Under these conditions, the output of the comparator will be low, since the
analog input (inverting input) is higher than the D/A output voltage (noninvert-
ing input). The control unit interprets this to mean that the SAR value is too low,
and it then leaves the MSB (fe 3) alone and also sets the next bit (b 2). The SAR now
holds the binary value of 1100, which converts to 7.5 volts at the output of the
D/A converter. Since this exceeds the value of analog input voltage, the compara-
tor output will go high. The control unit interprets this to mean that the SAR value
is too high.
The control unit then resets bit b 2 (since that is what caused the excessive
value) and sets the next most significant bit (bi). The SAR value of 1010 is now
applied to the D/A converter to produce a comparator input of 6.25 volts. This is
still higher than the analog input voltage, so the comparator output remains high.
The control unit again interprets this to mean that the SAR value is too large.
The control unit then resets bit b} and sets the next lower bit (& 0), thus yield-
ing an SAR value of 1001. This converts to 5,625 volts at the output of the com-
parator. Since this is still lower than the analog input, b Q will remain set. The
conversion complete signal is now generated, indicating a completed conversion.
The result (1001) is available in the SAR.
In general, the control unit starts by setting the most significant bit and mon-
itoring the output of the comparator. This bit will then be left set or will be reset as
a function of the state of the comparator. In either case, the same process is applied
to the next lower bit and so forth until the least significant bit is left either set or
reset. With each progressive step, the approximation gets closer. Regardless of the
magnitude of the analog input voltage (within the limits of the converter), it will
always take as many clock periods to convert the voltage as there are bits in the
converted number. In this example, the successively better approximations were
as listed in Table 8.4.
There is a striking similarity between the logic used during the successive
approximation process and the logic applied during a split-half troubleshooting
exercise. In both cases, each successive step reduces the number of options by one-
half.
There are many integrated forms of A/D converters that utilize the succes-
sive approximation technique. One such device is the ADC-910, which is a 10-bit
converter manufactured by Analog Devices, Inc. It provides a 10-bit result in 6
microseconds and is compatible with microprocessors. It should also be pointed
out that all functions represented in Figure 8.16, except for the comparator and