Page 122 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL ANALYSIS Ronald E. Best 79
■ For the active PI filter

(3.81)

The pull-in time becomes

(3.82)

When the passive or the active lead-filter is used, this formula gives acceptable results when
Δω is less than about 0.8 Δω .
0
P
Phase detector type 4a. When the PFD with voltage output is used as phase detector, we
have to develop another model for the pull-in process because the dynamic behavior of the
PFD differs greatly from that of all other phase detectors. As we have already seen, the output
signal of the PFD depends on the phase error in the locked state of the PLL. When the PLL is
out of lock, however, the output signal of the PFD depends on the frequency error (cf. Fig.
2.15). As explained in Sec. 2.4.4.1, the PFD has a tri-state output. We have seen in Sec. 3.9.1
that any loop filter cascaded with this type of PFD behaves as a real integrator (meaning it has
a pole at s = 0) when both flipflops of the PFD are in the 0 state, refer also to Eqs. (3.56)
through (3.58). Hence, the DC gain of all loop filters is (at least theoretically) infinite, and the
pull-in range Δω also becomes infinite. In practice, the pull-in range corresponds to the range
P
of frequencies the VCO is able to generate.
The pull-in time remains finite, of course, so we need a suitable approximation for T . First,
P
we will calculate the pull-in time T for the case where the passive lead-lag loop filter is used.
P
We assume again that the PLL is initially out of lock and the VCO operates at its center
frequency ω . The input radian frequency ω is assumed to be markedly higher than the
1
0
down-scaled VCO output frequency ω /N = ω ′. The initial radian frequency offset is
0 0
denoted Δω with Δω = ω − ω ′. This situation is sketched by the upper two waveforms in
0
1
0
0
Fig. 3.18. As explained in Sec. 2.4.4.1 and Fig. 2.12, the output signal u of the PFD then
d
toggles between the states 0 and 1. The third trace shows the waveform of u . It was assumed
d
that the PFD is powered by a unipolar supply so the logical “high” level is U , while the
B
“low” level is 0 V (ground). The centerline of the u signal represents the high-impedance
d
state of the PFD (Hi-Z). The average u signal is drawn as a dashed line. It has the shape of a
d
sawtooth signal. The average u signal is nothing else than the duty cycle of the PFD output. It
d