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Support Circuit Design 337

cuits instead of SRDs (PIN multipliers have similar characteristics to SRDs,
but are much cheaper).
While multiplication is a viable and common method of increasing the fre-
quency out of any oscillator, it should also be noted that phase noise will degrade
a signal by a minimum of 6 dB per frequency doubling. Even PLL outputs can be
multiplied to obtain almost any desired frequency, but at the expense of higher
phase noise, as well as decreased frequency resolution. In fact, the phase noise of
the frequency source feeding the input of the multiplier degrades by at least 20
log N at the multiplier’s output, where N is the amount of multiplication.

8.1.2 Frequency multiplier design
As discussed above, there are numerous multiplier circuit topologies that are
perfect for the particular frequency, cost, and multiplication desired. A few
simple-to-design multiplier circuits are presented below (see also Sec. 10,
“Wireless Design Software,” for the program Multfrq, which can automatically
design passive multipliers, and is available by free download from the Web).

MMIC multipliers. MMIC amplifiers can be adapted as odd/even harmonic fre-
quency multipliers by overdriving the MMIC’s input into saturation. To mini-
mize the output MMIC’s required drive level, it should have a low P1dB, and
the harmonic of choice should not be above the 3-dB bandwidth of the device.
Indeed, driving the MMIC into saturation—but not above its rated safe input
level—while also increasing the DC bias current will materially assist in opti-
mal harmonic generation. The DC bias current can be increased either by rais-
ing the MMIC’s V supply voltage or by decreasing its bias resistor value,
CC
R . This will place a comb of harmonics at the MMIC’s output, which may
BIAS
be picked off by a filter tuned to the desired harmonic. Proper spacing of the
filter from the MMIC’s output will maximize the exact harmonic of interest,
with the spacing determined empirically.
By combining all of the above MMIC multiplication design techniques, a
multiplication factor of up to 10 times the input frequency can be realized,
with a loss of only 30 dB from the fundamental input signal.

Snap frequency multipliers (Fig. 8.5). Step-recovery, or “snap,” diodes, function
by switching between two impedance conditions: low and high. This change of
state may occur in only 200 ps or less, discharging a narrow pulse that is quite
rich in harmonics.
Snap-recovery diode (SRD) frequency multipliers are operated only in very
high frequency circuits because of their high cost, the necessity to hand-tune
each SRD circuit, the 17 dBm input power required, and other difficult imple-
mentation issues as compared to PLLs or active harmonic multiplication.

1. First, choose the correct SNAP:
a. Lifetime rating on the SRD data sheet must be at least 10 times longer
than the period (1/f) of the input frequency (given in nanoseconds).

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