Page 340 - Complete Wireless Design

Support Circuit Design

Support Circuit Design 339

b. For C (or C ), use nominal value on data sheet for L calculation.
vr j D
c. Transition time (T ) must be less than one period (1/f ) of f (the final out-
t 0 0
put frequency) on data sheet (measured in picoseconds).
2. T f .
1
p 2 0
3. R 6.28 f L .
IN IN D
4. R 50 ohm.
G
5. RFC 600-ohm impedance at f , but capable of attenuating f as well.
IN 0
1
6. C
m
6.28 f R R .
IN G IN
R R
IDN.
G
7. L
M
6.28 f
IN
C
vr
8. C
T 2
(2f T )
IN p
C is provided on the diode’s data sheet. It is sometimes given as C .
vr j

T
1
9. L p 2 .
D C
vr
10. L L .
R D
1
11. C .
R 2
(2 f ) L
0 R
12. f f N.
0 IN
13. Tune the snap circuit. Since the diode’s output is a comb of frequencies, a spec-
trum analyzer is utilized to tune the SRD for maximum power output at the
desired harmonic. Insert the proper frequency and power ( 17 to 23 dBm)
at the SRD circuit’s input. Adjust C (input match), R (diode bias), and C
M 1 R
(line filter) until the desired output frequency is at maximum power, while
confirming that all subharmonics and harmonics are properly attenuated.
Odd-order Schottky diode tripler multiplier (Fig. 8.6). This is one of the easier
frequency multipliers to design for operation up to 600 MHz output, as pre-
sented by Wenzel. L and C form the input matching network, while blocking
1 1
harmonics from entering the input of the multiplier, as well as increasing the
input voltage to the diode (caused by this high-Q matching circuit transform-
ing the impedance and the voltage).
D and D are the nonlinear harmonic-generating devices. L is the DC
1 2 4
ground for the diodes, with the DC being created by rectification of the AC of
the input by D . L , C , L , and C shunt the undesired frequencies to ground,
1 2 2 3 3
while passing only the frequency of interest and matching the output (as with
most multipliers, the diode switching times will be degraded unless these
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