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4.2 / CACHE MEMORY PRINCIPLES 119

determine if the word is in the cache. If so, the word is delivered to the processor. If
not, a block of main memory, consisting of some fixed number of words, is read into
the cache and then the word is delivered to the processor. Because of the phenome-
non of locality of reference, when a block of data is fetched into the cache to satisfy
a single memory reference, it is likely that there will be future references to that
same memory location or to other words in the block.
Figure 4.3b depicts the use of multiple levels of cache. The L2 cache is slower
and typically larger than the L1 cache, and the L3 cache is slower and typically
larger than the L2 cache.
Figure 4.4 depicts the structure of a cache/main-memory system. Main memory
n
consists of up to 2 addressable words, with each word having a unique n-bit address.
For mapping purposes, this memory is considered to consist of a number of fixed-
length blocks of K words each. That is, there are M = 2 /K blocks in main memory.
n
3
The cache consists of m blocks, called lines. Each line contains K words, plus a tag of
a few bits. Each line also includes control bits (not shown), such as a bit to indicate

Line Memory
number Tag Block address
0 0
1 1
2 2 Block
3 (K words)
•
•
•

C 1
Block length
(K Words) •
•
(a) Cache
•

Block

n
2 1
Word
length
(b) Main memory
Figure 4.4 Cache/Main Memory Structure

3 In referring to the basic unit of the cache, the term line is used, rather than the term block, for two rea-
sons: (1) to avoid confusion with a main memory block, which contains the same number of data words as
a cache line; and (2) because a cache line includes not only K words of data, just as a main memory block,
but also include tag and control bits.