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122 CHAPTER 4 / CACHE MEMORY

Table 4.2 Elements of Cache Design

Cache Addresses Write Policy
Logical Write through
Physical Write back
Cache Size Write once
Mapping Function Line Size
Direct Number of caches
Associative Single or two level
Set Associative Unified or split
Replacement Algorithm
Least recently used (LRU)
First in first out (FIFO)
Least frequently used (LFU)
Random

computation, and the use of parallel algorithms. Cache design for HPC is quite dif-
ferent than for other hardware platforms and applications. Indeed, many researchers
have found that HPC applications perform poorly on computer architectures that
employ caches [BAIL93]. Other researchers have since shown that a cache hierar-
chy can be useful in improving performance if the application software is tuned to
exploit the cache [WANG99, PRES01]. 4
Although there are a large number of cache implementations, there are a few
basic design elements that serve to classify and differentiate cache architectures.
Table 4.2 lists key elements.

Cache Addresses
Almost all nonembedded processors, and many embedded processors, support vir-
tual memory, a concept discussed in Chapter 8. In essence, virtual memory is a facil-
ity that allows programs to address memory from a logical point of view, without
regard to the amount of main memory physically available.When virtual memory is
used, the address fields of machine instructions contain virtual addresses. For reads
to and writes from main memory, a hardware memory management unit (MMU)
translates each virtual address into a physical address in main memory.
When virtual addresses are used, the system designer may choose to place
the cache between the processor and the MMU or between the MMU and main
memory (Figure 4.7). A logical cache, also known as a virtual cache, stores data
using virtual addresses. The processor accesses the cache directly, without going
through the MMU. A physical cache stores data using main memory physical
addresses.
One obvious advantage of the logical cache is that cache access speed is faster
than for a physical cache, because the cache can respond before the MMU performs

4 For a general discussion of HPC, see [DOWD98].