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5.4 / RECOMMENDED READING AND WEB SITES 179

There have been two generations of improvement to the DDR technology.
DDR2 increases the data transfer rate by increasing the operational frequency of the
RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip. The
prefetch buffer is a memory cache located on the RAM chip. The buffer enables
the RAM chip to preposition bits to be placed on the data base as rapidly as possi-
ble. DDR3, introduced in 2007, increases the prefetch buffer size to 8 bits.
Theoretically, a DDR module can transfer data at a clock rate in the range of
200 to 600 MHz; a DDR2 module transfers at a clock rate of 400 to 1066 MHz; and
a DDR3 module transfers at a clock rate of 800 to 1600 MHz. In practice, somewhat
smaller rates are achieved.
Appendix K provides more detail on DDR technology.

Cache DRAM
Cache DRAM (CDRAM), developed by Mitsubishi [HIDA90, ZHAN01], inte-
grates a small SRAM cache (16 Kb) onto a generic DRAM chip.
The SRAM on the CDRAM can be used in two ways. First, it can be used as a
true cache, consisting of a number of 64-bit lines.The cache mode of the CDRAM is
effective for ordinary random access to memory.
The SRAM on the CDRAM can also be used as a buffer to support the serial
access of a block of data. For example, to refresh a bit-mapped screen, the CDRAM
can prefetch the data from the DRAM into the SRAM buffer. Subsequent accesses
to the chip result in accesses solely to the SRAM.

5.4 RECOMMENDED READING AND WEB SITES

[PRIN97] provides a comprehensive treatment of semiconductor memory technologies, in-
cluding SRAM, DRAM, and flash memories. [SHAR97] covers the same material, with more
emphasis on testing and reliability issues. [SHAR03] and [PRIN02] focus on advanced
DRAM and SRAM architectures. For an in-depth look at DRAM, see [JACO08] and
[KEET01]. [CUPP01] provides an interesting performance comparison of various DRAM
schemes. [BEZ03] is a comprehensive introduction to flash memory technology.
A good explanation of error-correcting codes is contained in [MCEL85]. For a deeper
study, worthwhile book-length treatments are [ADAM91] and [BLAH83]. A readable theo-
retical and mathematical treatment of error-correcting codes is [ASH90]. [SHAR97] contains
a good survey of codes used in contemporary main memories.

ADAM91 Adamek, J. Foundations of Coding. New York:Wiley, 1991.
ASH90 Ash, R. Information Theory. New York: Dover, 1990.
BEZ03 Bez, R.; et al. Introduction to Flash Memory. Proceedings of the IEEE,April 2003.
BLAH83 Blahut, R. Theory and Practice of Error Control Codes. Reading, MA:
Addison-Wesley, 1983.
CUPP01 Cuppu, V., et al. “High Performance DRAMS in Workstation Environments.”
IEEE Transactions on Computers, November 2001.
JACO08 Jacob, B.; Ng, S.; and Wang, D. Memory Systems: Cache, DRAM, Disk. Boston:
Morgan Kaufmann, 2008.
KEET01 Keeth, B., and Baker, R. DRAM Circuit Design: A Tutorial. Piscataway, NJ:
IEEE Press, 2001.