Page 206 -

Column decoder Column decoder Cell array Cell array memory bank 1 memory bank 0 (2 Mb 8) (2 Mb 8) DRAM DRAM Row decoder Row decoder Sense amplifiers Sense amplifiers DQ0 DQ1 DQ2 signal Control generator DQ3 DQ4 circuitry DQ5 Data control DQ6 Data I/O buffers DQ7 MR DQM Column decoder Column decoder CAC Column address counter Cell array Cell array MR Mode register memory bank 3 memory bank 2 Refresh counter RC (2 Mb 8) (2 Mb 8) DRAM DRAM R

CKE buffer CLK buffer Address buffers (14) RC CAC CS RAS decoder CAS Command WE Synchronous Dynamic RAM (SDRAM)

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A12 A13 A10 Figure 5.12
CKE CLK

175