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12.3 Layout Styles 537

12.3 LAYOUT STYLES

There are several major design styles that are identified by the standardization
constraints imposed in the design at the geometrical level. Each style imposes its
unique set of constraints on the design method as well as on the tools used for the
design and testing.
The standard-cell, gate array, and sea-of-gates styles are called semicustom
approaches by the silicon vendors, since the circuit design involves only some of
the mask layers or uses a vendor-supplied cell library. The latter two approaches
are based on prefabricated wafers that can be personalized by using a few inter-
connection layers. In other layout styles all mask layers are specified by the
designer and these styles are therefore called full-custom styles by the silicon ven-
dors. These terms are somewhat confusing, are irrelevant from the system
designer's point of view, and are therefore not recommended. A more useful classi-
fication divides the layout styles along the imposed standardization constraints
placed on the building blocks.

12.3.1 The Standard-Cell Design Approach
In the standard-cell approach the designer builds the system by using cells that are
stored in a cell library that often is provided by the silicon vendor. Most cell libraries
contain only simple gates and flip-flops, but there is a trend that the vendors also
include more complex logic and even analog building blocks. The basic idea was orig-
inally to provide the designer with a route to design VLSI circuits in the same way
as was used for design with SSI and MSI circuits. The standard-cell approach is
suitable for mapping existing designs, built with now outdated SSI and MSI compo-
nents, onto silicon. Of course, it is also used for new designs. The approach is simple
and therefore an economically important approach to VLSI design.
The simplicity comes from the similarity to conventional (older) design tech-
niques and the standardized floor plan. A typical floor plan for a standard-cell
design approach is shown in Figure 12.6 [4, 14]. The cells implementing the logic
circuits are placed in rows, and routing areas, also called routing channels, are pro-
vided between the rows. Notice that the heights of the routing channels, which are
often referred to as the channel widths, can be selected according to the require-
ments. The height of the cells is fixed while the cell length varies from cell to cell.
In this approach the designer enters the design by selecting the appropriate
circuits (logic primitives) from a library and by providing a netlist with their inter-
connections. The cells have output buffers that can drive a few other cells so the
designer is only required to check a maximum fan-out design rule. The design is
typically validated by logic and simple timing simulations. Automatic CAD tools
are then used to map the design onto silicon. The tool selects the proper position-
ing of the cells and performs the wiring. The placement of the cells is restricted in
order to simplify placement and to reduce the required number of geometrical
variations of a cell.
In a standard cell the power and grounds are distributed using horizontal
wires inside the cells so that abutting cells automatically make the necessary
connections. The power is fed from the end of each row of cells. Inputs and out-
puts of the cells appear at the top and bottom. The wiring between the cells is