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12.3 Layout Styles 539
Custom cells (for example, RAM and ROM) as well as analog cells can be
incorporated. Appropriate I/O drivers can be selected. A significant
percentage of the power is often dissipated in the I/O drivers.
The cell library is fully dependent on a specific VLSI process.
12.3.2 The Gate Array Design Approach
A simple layout style that significantly reduces processing costs is the gate array
design approach [7]. In this approach, all but the last few mask layers are pre-
defined by the silicon vendor and the designer is presented with an array of gates
(transistors), as shown in Figure 12.7.
