Page 556 - DSP Integrated Circuits

12.3 Layout Styles 541

12.3.3 The Sea-of-Gates Design Approach
The sea-of-gates design approach is a variation of the gate array theme. The areas
dedicated for wiring have been removed and the gate pattern has been made more
uniform. The device density is therefore much higher than for ordinary gate
arrays. The wiring is done over unused devices, and contacts to active devices are
created whenever needed. Performance approaching that of full-custom design is
obtained because of the high device density and ease of wiring. Figure 12.8 illus-
trates the basic idea for a cell that implements a three-input NAND gate. The sec-
ond metal layer is used to customize the array. A drawback of both gate arrays and
sea-of-gate arrays is that all devices have the same W/L ratio. Some CMOS logic
circuit styles (for example, dynamic logic, transmission gate flip-flops, ROMs, and
RAMs) require transistors of different sizes.

Figure 12.8 Sea-of-gates layout of a three-input NAND gate

High-speed, sea-of-gates arrays with more gates than the corresponding gate
arrays are available. The number of equivalent gates on both gate and sea-of-gate
arrays increases very rapidly with the shrinking of the geometries. Sea-of-gates
2
arrays have achieved up to 1600 two-input NAND gates per mm , ROMs with 17
2
2
kbit/mm , and static RAMs with 1.1 kbit/mm using a 0.8-um process with three
metal layers.
12.3.4 The Unconstrained-Cell Design Approach
The unconstrained-cell design or macrocell design approach allows arbitrary
shapes and placement of the building blocks. Typically, the layout of the building