Page 555 - DSP Integrated Circuits

Gate arrays are relatively inefficient in utilization of chip area for two main
reasons. Firstly, gate arrays come only in standard sizes. It is necessary to select a
chip that contains more gates than needed. Typically, less than 80% of the avail-
able gates can be used. Secondly, the routing areas are made wide in order to
accommodate a large number of wires. This means that the routing areas are
wider than necessary.
Gate arrays provide the means by which a large portion of the general-purpose
logic used in most large electronic systems can be combined into a single-package
solution. Both the standard-cell and the gate array approaches reduce the
designer's layout work by unloading it onto a computer.
The customization of the gate array requires only a few processing steps.
Hence, the turnaround time can be very short, since the silicon vendor can stock
prefabricated gate array wafers. The total manufacturing cost for a gate array
design depends mainly on the chip size, packaging, and processing cost—and the
processing cost is very low.
For large-volume applications, the relative inefficiency with respect to chip
area may become significant. Larger chips result in higher system costs due to
higher chip cost since there are fewer working chips on each wafer and a larger
and more expensive package must be used. A more area-efficient design, using a
more expensive design approach, may therefore more than balance the higher
design cost. The gate array approach is therefore an economical alternative for
low- and medium-volume systems.
BiCMOS technologies are particularly suitable for gate arrays because of
their ability to drive nodes representing large capacitances, which are characteris-
tic for gate arrays. The bipolar devices are used for I/O drivers, clock drivers, and
time critical circuits.
Gate arrays are inefficient for realization of large memories. Special gate
arrays are therefore provided with a RAM. Gate arrays with analog building
blocks are also available. Fast gate arrays based on GaAs can accommodate more
that 30,000 equivalent two-input NAND gates while dissipating 8 W. Silicon-based
gate arrays achieve much higher gate counts. For example, Texas Instruments has
a BiCMOS gate array with 150 kgates in a 0.8-um process.
Characteristics for the gate array design approach are:
Q The layout pattern of the transistors is fixed. Only the placements of cells,
customization of transistors into cells, and routing are required.
Q The design involves mainly schematic or netlist entry followed by logic
verification-validation. The placements (position and rotation) of cells and
wire routing including simple simulation, fan-out, and wire length
checking are done by special tools. Normally, the vendor does the detailed
timing analysis and checking of the layout for design rule violations.
Q The device density and the switching speed are lower than for standard-
cell designs, but this is often compensated for by the availability of more
advanced processes with smaller geometries.
Q The turnaround time is shorter and the processing cost is much lower
than for standard-cell designs.
G Changing vendor or VLSI process is simple. Often, only the timing needs
to be checked by simulation.