Page 559 - DSP Integrated Circuits

544 Chapter 12 Integrated Circuit Design

tool. Standardization is only used at the lowest layout level to reduce the design
space. It takes the form of design rules that impose geometrical and topological
constraints on the layout. These constraints originate from two sources:

Limitations in the manufacturing process—for example, misalignment
among mask layers, minimum width, and spacing of features.
Physical limitations of circuits such as electromigration, current densities,
junction breakdown, punch through, and latch-up.
Often, a Manhattan geometry is imposed on the layout. In this stan-
dardization of the layout, the wires are required to run only horizontally or verti-
cally. The Manhattan layout style significantly simplifies the checking of the
design rules. Many design rule checkers only accept Manhattan layouts.
Characteristics for the unconstrained-cell approach are:
Generally, no restrictions are put on the shape, area, and placement of
modules or the wire routing. The layout of the low-level cells is done in
detail and allows all aspects of the cells to be optimized, but it is costly in
terms of design time. This cost may be reduced by using automatic design
tools for the cell design.
The design involves not only schematic and netlist entry, but also detailed
layout, design rule checking, logic and electrical simulation, etc. As
opposed to the semicustom approaches, the designer is responsible for the
whole design.
Sophisticated software is required to generate the building blocks.
The potential device density and switching speed are very high. Typical
device densities for a double metal, 0.8-um CMOS process are in the range
2
of 6000 to 11000 transistors per mm . However, device density, normalized
with respect to the shrinking geometry, which are achieved in micro-
processor chips are continuing to decrease [12]. The reason for this decline
in device density is to be found in the inefficient design methodologies and
design tools that are being used.
Turnaround time and cost are the same as for standard-cell designs.
The design time may be long and less well controlled.
Changing vendor or VLSI process may be difficult, but may be somewhat
simpler if automatic or semi-automatic layout tools are used.
Digital and analog circuits can be mixed. Medium- to relatively large-size
memories can be implemented in a standard process for digital circuits.

12.3.5 The Unconstrained Design Approach
This is the most powerful and flexible design method. The designer has full free-
dom to specify all design parameters, transistor sizes, placement, routing, etc. This
freedom gives the fullest control over area, speed, power consumption, etc., both
for the devices and for the whole chip. However, because of the large flexibility, the
design effort becomes very large and costly and the lack of standardization makes
many design tools unusable. Therefore, the unconstrained design approach in
practice is used only for critical circuits where performance is of major concern—
for example, RAM and ROM cells.