Page 165 - Embedded Microprocessor Systems Real World Design

Edge- and Level-Sensitive Interrupts

An interrupt input can be edge or level sensitive. A level-sensitive interrupt is
recognized by the processor whenever the interrupt pin is in the active state. An
edge-sensitive interrupt means that the processor responds to a rising or falling
edge on the interrupt pin. Some processors and interrupt controllers have inter-
rupt inputs that can be programmed as either level or edge sensitive. We’ll address
edge- and level-sensitive interrupts in more detail later in the chapter.

Interrupt Priority

Interrupts usually have a priority. The priority determines when an interrupt is
serviced. A higher-priority interrupt takes precedence over a lower-priority one if
both are asserted at the same time. Some processors permit nested interrupts. When
enabled by software, nested interrupts allow an ISR itself to be interrupted by a
higher-priority device. Interrupts from lower-priority devices are ignored until the
higher-priority ISR is completed.
Different types of processors have different priority schemes. The 68000 family
parts, for example, allow a peripheral requesting an interrupt to assert its own
priority; it is up to the hardware engineer to make sure there are no conflicts. The
Intel 8259 interrupt controller has several interrupt input pins, with programma-
ble priority. The priority of interrupts inside an embedded processor sometimes is
fixed, sometimes programmable.

Interrupt Hardware

Hardware to implement interrupts varies with the processor and the peripheral
doing the interrupting. We will look at the simplest cases first and work up.
The simplest interrupt is a single pin on the microprocessor. The 80188, for
example, has four interrupt inputs: INTO, INTl, INT2, and INTS. (There is a fifth,
NMI, which we’ll discuss later.) These interrupts may be programmed to be either
level or edge sensitive. Each pin, when activated, causes the processor to vector to
a specific address, as shown in Table 5.1.
The code at the interrupt address is usually a jump to the actual ISR somewhere
else. The vector, as mentioned earlier, is provided by an interrupt controller inside
the 80188.

146 Embedded Microprocessm Systems