Page 167 - Embedded Microprocessor Systems Real World Design

a vector value on the data bus. In some early processors, such as the 8085 and 280,
the vector was actually an instruction. These processors include several 1-byte
instructions that force the processor to a specific address in low memory, and the
interrupt controller typically would provide one of those instructions in response
to an interrupt acknowledge. Other processors expect a number, which is used as
a pointer into a table, usually in low memory, that contains the jump instructions
to the IS&. (The 280 actually supports both schemes.) The 8086 family, for
example, reserves the first 1024 bytes of code space, from 00000 to 003FF, for the
interrupt table.
Using external vectors on processors that have that capability is the most flexi-
ble interrupt scheme, but it also requires more hardware than other methods. Each
peripheral in this scheme must include the hardware to recognize interrupt cycles
and provide the correct vector.

Interrupt Bus Cycles

When using an external vector, most processors perform an interrupt acknowledge
cycle that is similar to other bus cycles, but with different control or status signals.
The 8086, for example, performs a bus read cycle but with the interrupt acknowl-
edge (-INTA) signal replacing -RD and with a different status indication. The
68000 asserts -DS normally, and only the status bits indicate that the bus cycle is
an interrupt acknowledge.
Some designs use an interrupt IC that has several discrete interrupt inputs but
interfaces to the single processor interrupt line. These ICs produce the interrupt
request to the processor and, when the interrupt is acknowledged, return the inter-
rupt vector corresponding to the highest-priority interrupt pin activated. The 8259,
typical of interrupt controller ICs, has eight interrupt inputs and is designed to
interface to Intel processors.

Daisy-Chained Interrupts

Some designs use daisychained priority interrupts, which are illustrated in Figure
5.3. The interrupt input in this scheme, usually open collector, is driven by all the
interrupting peripherals. When any peripheral needs to interrupt the processor, it
activates the interrupt line. Each peripheral also has a priority in and a priority out.
The priority in is connected to the next highest peripheral in the daisy chain or
tied active for the highest-priority device. The priority out is connected to the next
lowest peripheral. If any particular peripheral is not requesting an interrupt, its

148 Embedded Micropomsur Systems