Page 170 - Embedded Microprocessor Systems Real World Design

Level-Sensitive Interrupts
When using level-sensitive interrupts, remember that the processor will see an
interrupt when and only when the level-sensitive interrupt pin is in the active state.
This can be an advantage or a disadvantage. If the interrupt gets stuck in the active
state, the processor will service the interrupt, exit the ISR, and immediately reenter
the ISR. On most processors, nothing else will get done, as the processor loops con-
tinuously in the interrupt code. When using level sensitive interrupts, make sure
they cannot get stuck. If a level-sensitive interrupt comes from an external device
or system, be sure that turning off the power to that device will not leave the inter-
rupt in the active state.
Devices that generate level-sensitive interrupts usually need some mechanism
that allows the processor to clear the interrupt request before exiting the ISR. In
some cases, this may happen automatically, such as when the processor reads a byte
from the peripheral. In other cases, the software may have to clear the interrupt
by writing to an address, toggling a port bit, or performing some other operation.
The reverse of a stuck interrupt also can occur with a level-sensitive interrupt.
If the interrupt is asserted and removed before the processor services it, the inter-
rupt (usually) will never be recognized. This can occur if the interrupt is not
latched and the processor has interrupts disabled or if the processor is busy ser-
vicing a higher-priority interrupt that takes longer to handle than the active time
of the missed interrupt.
Level-sensitive interrupts can be useful if multiple devices share the interrupt.
The devices can each assert the interrupt when necessary. If two devices assert the
interrupt at the same time, the processor will service the first one, exit the ISR,
reenter the ISR, and service the second. Note that in processors that have a single
interrupt input and an external controller or that use daisy-chained interrupts, the
single interrupt input is level sensitive.

Edge-Sensitive Interrupts
Edge-sensitive interrupts are ideal for counting events. The processor accepts the
interrupt only on the edge. Some processors have a requirement that the interrupt
go to the active state and stay in that state until serviced. For these devices, pulsing
the interrupt to the inactive state generates the interrupt. For example, the 80188
interrupt inputs, when programmed to be edge sensitive, must go high and remain
high until serviced by the processor. The interrupting device can leave the line high
and pulse it low to generate an interrupt. The line can be left high between inter-
rupts. If you use this technique, be sure that the inactive pulse width meets the
minimum requirement for the processor or interrupt controller IC. This time
usually is measured in clock cycles.
Figure 5.5 illustrates the difference between edge- and level-sensitive interrupts.

Interrupts in Embead Systems 151