Page 175 - Embedded Microprocessor Systems Real World Design

timer system has one interrupt, a timer interrupt that occurs 250 times per second.
Servicing that interrupt involves the following sequence (Appendix A lists the full
pseudocode) :
Increment the 1/250second time counter.
If the display should blink, do it at half-second intervals.
At the 1-second rollover, decrement the current time.
If the current time rolls over to OO:OO, set a flag to tell the polling loop about it
and load the next (off or on) time.
Write the next display digit to the display and enable the proper digit. (This scans
the display.)
If keys are pressed on the keypad, debounce them and set the appropriate flag
for the polling loop.

On returning from the ISR, enabling the system to accept further interrupts may
be as simple as executing an interrupt return instruction that is similar to the ordi-
nary subroutine return but also reenables interrupts. Other processors require a
separate interrupt enable (reenable) instruction prior to an ordinary subroutine
return instruction.
Some interrupt controllers, both those inside and outside the processor IC, need
to be told when interrupt processing is complete by writing a value to some address.
In this case, just returning from the ISR is insufficient. Returning to the code that
was interrupted also means restoring the state of the machine. Any registers that
were used in the interrupt should have been saved on the stack and restored before
returning.
When an interrupt occurs, the processor saves the return address on the
stack (usually). (The stack was described in Chapter 4.) The usual practice for
entering an ISR is to save all the processor registers, just like any other subroutine.
However, as Chapter 4 discussed, limitations on stack size sometimes make this
impractical.
An ordinary (non-ISR) subroutine can be called with the knowledge that some
registers will be changed during execution. An ISR cannot do this, as there is no
way to know what registers are being used by the polling loop or a higher-priority
ISR when the interrupt occurs, The ISR must save all registers that it uses unless
the software engineer can be sure that a particular register is used nowhere else.
This is a dangerous practice unless you can dedicate certain registers only to the
ISR.
In addition to limiting stack size, some processors make it impossible to save reg-
isters on the stack. The PIC17C42, for example, has a l6level stack and no PUSH
or POP instructions. The stack is used for return addresses only. Values that must
be saved, such as register contents, must be stored in discrete RAM locations as
described for subroutines in Chapter 4.

156 Embedded Microprocessor Systems