Page 180 - Embedded Microprocessor Systems Real World Design

3. Store the result back at qz. (CPU now stores 01 in 9%. ISR operation is
overwritten.)
This is a contrived example, but I have seen this exact scenario occur with an
1/0 register more than once. Avoid this pitfall. It can be extremely difficult to find,
as it can be very intermittent. This leads to what I call the first rule of interrupts:

Wherever possible, avoid having interrupts that write memory or VO
locations that are also written by the polling loop or by other interrupts.
Locations written by the polling loop should be read by the ISR and vice
versa.

The exception is certain semaphores. The pool timer ISR, for example, sets
semaphores when a key is pressed. If the polling loop does not clear the semaphore
(if it is in a mode in which that key is ignored), the ISR resets the semaphore when
the key is released. This is a “safe” violation of the rule since the key press will never
be so fast that the polling loop misses it. It is safe to violate this rule on occasion,
but be sure you know it is really safe. Again, problems in this area can be very hard
to find.
In cases where you must violate this rule because of hardware constraints (an
1/0 expander IC shared between the polling loop and the interrupt code, for
example), disable interrupts before the write operation and reenable interrupts
after the write. This will keep an ISR from altering the contents in the middle of a
write. The following is the original pseudocode sequence, bracketed by the
disable/enable:

Disable interrupts.
1. Read location qz.
2. OR the value 01 with the data from qz.
3. Store the result back at qz.
Enable interrupts.

This, by the way, is the reason why common registers such as the 8051 accumula-
tor must be saved in the ISR. If the polling loop just did an AND operation on the
accumulator to check a bit and then the ISR changes the accumulator, the polling
loop would make the wrong decision.
One way to avoid problems with shared hardware is to have a pair of mask
bytes. For example, say an %bit register or output port is written by the software.
The lower 4 bits are connected to status LEDs and the upper 4 bits turn four sole-
noids on and off. Let us also say that the polling loop controls the LEDs and an
ISR controls the solenoids. This is an obvious case where a potential conflict can
occur.

Intermpts in Embedded Systems 161