Page 179 - Embedded Microprocessor Systems Real World Design
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The only exception is when you know some interrupts are mutually exclusive.
                   For example, if you are using a half-duplex serial interface, you know you will not
                   have receive and transmit interrupts simultaneously. Similarly, if your system uses
                   either  an Ethernet or RS232 interface but never both, you can probably assume
                   that you don’t have to worry about those interrupts stacking up.


                   Stuck interrupts
                   As  mentioned  earlier, a stuck level-sensitive interrupt can cause the processor to
                   hang up in the ISR. It is possible to detect a stuck interrupt (say, so you can shut
                   off the motors when it occurs). If you know that the interrupt rate is slow enough
                   that the polling loop should execute several times between interrupts, set a flag on
                   each pass through the polling loop. The ISR checks the flag and if it is not set, the
                   interrupt must be stuck. If  the interrupt can occur more than once for each pass
                   through the polling loop, add a counter to the ISR and increment the count each
                   time that the ISR executes when the flag is not set. If the count ever reaches a value
                   higher than should occur in normal operation, the interrupt is stuck. With either
                   approach, be sure to take into account other ISRs that may delay execution of the
                   polling loop.


                   The Shared Memory or VO Trap
                   Look at the following numbered lines of pseudocode:

                   1. Read location xyz.
                   2.  OR the value 01 with the data from xyz.
                   3.  Store the result back at xyz.
                     Now look at the following interrupt code:

                     OR  the value 2Oh into location xyz.
                     Return.

                     If  xyz contains, say, 00, and the first code (steps 1 to 3) is executed, followed by
                   the interrupt,  the result will be 21 in  xyz.  If, however, the interrupt occurs while
                   the processor is between lines 1 and 2 or 2 and 3, the result will be 01 in xyz. The
                   operation performed by  the interrupt is overwritten by the code. You can see this
                   if you rewrite the original pseudocode with the ISR code in the middle:
                   1. Read location xyz.  (CPU reads 00)
                   2.  OR  the  value  01  with  the  data  from  xyz.  (Data = 01, but  not  stored  in  xyz
                     yet.)
                     -Interrupt  occurs here-
                     OR the value 20 h into location xyz.  (This is ISR code; ISR leaves 20 h in xyz.)


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