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I      1                 I
                INTERRUPT 1
                INTERRUPT 2                            I        I
                                                                        I
                SHARED INTERRUPT                                        I
                                                   -
                TO MICROPROCESSOR           7
                ISR FOR INTERUPT 1           I
                                                                        I
                ISR FOR INTERRUPT 2                      0
                                                                        I
                                                                       f
                                                             ISR 2 OCCURS WHILE ISR 1 IS STILL HIGH
                                                             MICROPROCESSOR SEES ONLY Oh€ EDGE
                                                             CAUSED BY ISR 1. AND INTERRUW 2 IS
                                                             NEVER SERWCED

                Figure 5.6
                Shared Edge-Sensitive Interrupts.


                   Another method to handle this problem  is  to arbitrate the interrupt input so
                that no device can request an interrupt while the line is active. Each interrupting
                device must hold the line active by using a resettable flipflop or something similar
                until the processor clears it. The software does not clear the interrupt line until it
                has serviced the interrupt and is ready to accept another. Most edge-sensitive inter-
                rupt circuits permit the internal interrupt to be cleared before another actually is
                enabled, which keeps the ISR from being a reentrant.
                   A  single device  connected  to  an  edge-sensitive interrupt  can  have  the  same
                missed interrupt problem  as multiple  devices if  it generates interrupts at a rate
                faster than the processor can service them.
                   Many  processors, such  as  the  80188, have  timer  inputs  that  can  be  used  as
                interrupts. The timer is programmed to count external edges on the input pin and
                generate an interrupt on rollover. The timer is then loaded with a count that is one
                less than the rollover value. The first edge causes a rollover and generates an inter-
                rupt. The ISR must reload the counter for the next interrupt. If the timer function
                is not needed, the input can function as an interrupt. Even if the extra interrupt
                is not needed because you ran out of interrupt inputs, using a timer input as an
                interrupt can be useful in some applications. If  it is essential to know if an inter-
                rupt is missed, this can be determined by  looking at the  timer in  the ISR. If  no
                interrupts are missed, the timer will have rolled over to zero. If one or more inter-
                rupts were missed, the  timer will  keep incrementing them and the value will  be
                greater than zero.
                   If  you have a use for this technique, remember that some timers can be pro-
                grammed either to keep incrementing after a rollover or to roll over and stop. Be
                sure you program the timer to keep going after a rollover. Figure 5.7 shows a timing
                diagram of the use of a timer as an interrupt source.



                Interrupts in Embedded Systems                                       153
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