Page 166 - Embedded Microprocessor Systems Real World Design

Table 5.1
801 88 Interrupt Vector Addresses.

Interrupt Vector Address

INTO 0003oh
INT1 00034h
I NT2 00038h
I NT3 0003Ch

The software may enable any, all, or none of these four interrupts, and it deter-
mines whether the interrupts are level or edge sensitive. In some processors, such
as the PIC 17C4x, interrupt pins can be used for functions other than interrupts,
and this is under software control as well. In general, most processors have the
ability not only to enable and disable specific interrupts but also to disable all inter-
rupts at the same time.
The second type of interrupt is generated by internal peripherals. The 80188
internal peripherals that can generate interrupts include two DMA controllers
and three timers. Other processors and other versions of the 80188 have differ-
ent internal peripherals, such as universal asynchronous receiver/transmitters
(UARTs) .
Internal interrupts work much the same way as external interrupts. Some event,
such as a timer rollover, occurs, and an interrupt is generated to the processor. Like
the external interrupts, these usually have a predetermined interrupt vector
address. The software must enable the peripheral device and enable interrupts
from the device. Like interrupts from the external pins, these interrupts are
handled and the corresponding vectors produced by the internal interrupt
controller.
Sometimes internal interrupts are shared. That is, multiple devices may share a
single interrupt source and vector. The timers in the 80188 work this way-all three
timers use the same interrupt. The ISR must read the timer status bits to determine
which timer (or timers) generated the interrupt. Similarly, the PIC 17C42 has
several internal peripherals that can generate interrupts but only three interrupt
vectors, so several peripherals must share an (internal) interrupt signal and vector.
When a peripheral interrupt occurs on the shared line, the ISR must poll the inter-
rupt status bits to see which peripherals are requesting service. The PIC 16C6x
series has only one interrupt vector-all interrupts require polling to determine
the source unless only one source is enabled.
The next level of interrupt complexity involves a vector provided by the periph-
eral. In this scheme, the peripheral interrupts the processor, and the processor
acknowledges the interrupt. When the acknowledge occurs, the peripheral places

Interrupts in Embedded System 147