Page 84 - Embedded Microprocessor Systems Real World Design

to support only &bit access to the device, using 8 bits of the data bus. If the soft-
ware attempts to perform a word write or a byte write to the wrong address, the
result is undefined. Interfaces like this normally do not attempt to cover all the
cases, since the software can be written to avoid invalid accesses.

Data Bus Loading

A microprocessor is specified to drive a particular DC loading (sourcing or sinking
current) and a particular capacitance loading. A common mistake is to ignore these
parameters and assume that the processor will drive the bus. This is a dangerous
practice, especially if a failure is likely to result in the engineer having to fix it in
an unsavory place, like an oil field or a country where you should not drink
the water. Bus loading problems can result in much the same sort of symptoms
as setup/hold-time violations. In fact, bus loading problems can cause setup and
hold-time problems because they change processor timing. A microprocessor is
specified to meet its performance characteristics with maximum DC sink and
source currents and with a maximum load capacitance. AMD’s version of the
80C188, for example, specifies a sink current of 2 mA and a capacitance drive capa-
bility of 1OOpF. If you exceed these numbers, the performance of the part starts
to degrade.
When the standard interface logic was LSTTL or FITL, I would usually find that
loading problems in designs I reviewed revolved around DC loading issues. Now
that the world has shifted primarily to CMOS, I see more problems with capaci-
tance. I think designers look at the extremely low leakage of CMOS inputs and just
forget that those inputs have capacitance. Some parts, such as the 8OC188, have a
derating chart for capacitance, which shows how much the outputs are slowed by
added capacitance beyond the specified value. However, in all cases, regardless of
whether it is specified, excessive loading can cause problems.
To calculate DC loading, add the maximum sink and source currents required
by all inputs and compare them to all the outputs (including bidirectional devices).
The sum of the input currents must not exceed the capability of the device with
the smallest output drive capability. On CMOS devices, check not only the output
current capability but what sink current does to the output voltage. The output
current of some CMOS devices is specified at TTL level voltages. If one of those
devices is driving an IC that requires CMOSlevel input voltages, there may be a
problem. If the total DC loading pulls the output of the first device down, the
second part may not see the correct value. Capacitance loading is similar. Add up
the input capacitance (sometimes specified as 1/0 capacitance for bidirectional
devices) and compare it to the drive capability for each device that must drive the
bus. The total capacitance should be less than what the device with the lowest drive

68 Embedded Microp-ocessor Systems