Page 81 - Embedded Microprocessor Systems Real World Design

timing requirements. You might see this if the peripheral with extended hold
requirements is memory-mapped and the processor performs a word write as a pair
of back-to-back byte writes.
The second, and simpler, method for extending the data hold time also is shown
in Figure 2.18. Here, a wait state is used to extend the processor write cycle. The
-WR pulse to the peripheral device does not connect directly to the processor
-WR signal but instead goes through some intermediate logic. This logic termi-
nates the -WR signal to the peripheral early in the cycle when the wait request is
removed. Since the processor will extend the cycle one clock past this point, the
data will be held on the bus for the peripheral device. This ensures that the data
hold-time requirement is met. It also guarantees that the processor will not perform
a second write that violates the chip timing.

8- Versus 16-Bit interfaces

Some processors are available with both 8- and 16-bit external interfaces. For
example, the 80188 uses the same microprocessor core as the 80186. However, the
external interface to memory and 1/0 is only 8 bits wide on the 80188, versus 16
bits on the 80186. Similarly, the 68008 microprocessor (now obsolete) had a 16-bit
68000 CPU core but interfaced to external memory and 1/0 devices via an &bit
bus. The 68001 has a selectable 8- or 16-bit bus. The SiemendInfineon C167 can
be programmed for either €4- or 16-bit external memory operations.
The drawback to using an 8-bit bus is performance. While the internal CPU is
the same as the 16-bit sibling, external access is slower. A processor with an &bit
external interface requires two memory cycles to get a 16-bit word, whereas the 16-
bit bus can get a word in one cycle.
So why would anyone want to use a processor with an &bit bus? Cost. Using a
16-bit bus requires two of everything. EPROMs and RAM must be 16 bits wide. Your
program may require only 1K of code space and 256 bytes of RAM, but you still
need a 16-bit interface to the processor, which means two (or more) RAM and
EPROM chips.
Some RAM and ROM ICs feature 16-bit data buses, but they typically are more
expensive than their &bit counterparts. In addition, many peripheral ICs only have
an 8-bit bus, which gives the 16-bit processor less of an edge. On the other hand,
some peripherals require 16-bit interfaces, which precludes using an &bit proces
sor. An &bit processor could be used, but only with data latches and external logic
to turn two &bit cycles into a single 16-bit cycle at the peripheral.
The 16-/8-bit concept also applies to other bus widths. The Intel 8OC960SA is a
l6bit multiplexed-bus version of the 32-bit 80C960. The 386EX is a l6bit bus
version of the 386 processor, optimized for embedded applications. Both the
80C960 and the 386EX use the same processor core as the larger parts they are
derived from; only the external bus is narrower.

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