Page 85 - Embedded Microprocessor Systems Real World Design

specification can tolerate. If derating curves are provided, they can be used to deter-
mine whether access times are degraded enough to be a problem.
If a loading problem is discovered, the simplest fix is to add a buffer to the data
or address buses. This isolates the processor bus from the peripherals that load it.
The problem with a buffer is that it adds delay to the system. If timing is marginal,
a faster EPROM, for example, may be required.
Note that adding a buffer may just move the problem around. All the periph-
erals have DC and capacitance loading specifications, too, and adding a buffer may
prevent a processor problem but leave a peripheral IC with a problem.
In the case in which a buffer fixes a problem with the processor but leaves a
peripheral with a problem, the bus may need to be split. This means that two or
more separate data buses are needed, each with a separate buffer. One simple way
to split the bus is to have output-only drivers. This technique is useful if there are
a large number of discrete output registers. All the registers are tied to one common
bus, which is buffered from the processor bus with a unidirectional buffer. The
processor sees only the load of the buffer, and the buffer is selected to be able to
drive the register bank. The advantage to this method is that the buffer can be
enabled all the time, eliminating the control logc.
Figure 2.20 shows a multichip design that uses a split bus and a unidirectional
buffer. For fastest access, the EPROM and RAM are connected directly to the
processor data and address buses. Lowdrive peripherals are grouped with the
EPROM and RAM on the processor bus. A second group of peripherals is con-
nected to a second bus through a bidirectional buffer. A bank of registers is driven
from a unidirectional buffer.
Regardless of what kind of buffers are used, the following rules must be obeyed:

Adding buffers requires additional control logic to enable the buffers and control
the direction of data flow. Be sure that the logic, especially if it’s in a PLD, has
all the inputs needed to determine when to turn a buffer on and change the
direction.
Whether using one buffer or multiple buffers, be sure that the control logic
allows each buffer to drive the bus only when the peripherals it controls are
accessed. Simultaneously enabling two buffers causes bus contention, which can
cause intermittent operation and even failure of the buffer ICs.
Bus contention also can be caused if a buffer is enabled while the processor or
a peripheral is driving the data bus. On a processor with a multiplexed data bus,
driving the bus with a buffer while the processor is trying to latch a PROM address
can be disastrous. Avoid that condition. Check the logic that enables the buffers
to be sure they are not enabled at the wrong time, and check buffer output
turnoff time to ensure that it is not too slow for the processor.
The data bus must propagate through the buffer, so add the propagation delay
of the buffer to EPROM, RAM, and peripheral access time calculations. When

Hardware Design 1 69