Page 270 - Engineering Digital Design

6.1 INTRODUCTION AND BACKGROUND 241

This limit is called the fan-out of a given device and is, in effect, the worst-case loading
specification for that device. The fan-out limit is usually given in microamps (juA). If the
fan-out limit of a device is exceeded, the signal can be degraded. MOS circuits are least
affected by fan-out restrictions, whereas members of the bipolar families are dramatically
affected by such restrictions. Propagation delay is essentially unaffected by fan-out limita-
tions.
The maximum number of inputs permitted to control the operation of a digital device
(usually a gate) is called the fan-in. Thus, a gate with four inputs has a fan-in of 4. In
general for CMOS gates propagation delay increases with increasing fan-in. Fan-in and its
consequences are discussed in Subsections 3.6.2 and 3.6.3 and in Section 4.10.

Cost The cardinality or cover of a function is a measure of the cost of that function.
Design area is also a measure of the cost of a function and is called area cost. Thus, the
cardinality or design area of a function can be given a monetary value, and this is what
is of particular interest to manufacturers of digital devices. But there are more factors that
contribute to the monetary cost of an 1C. To one extent or another all of the factors previously
mentioned directly or indirectly affect the cost of an 1C. Appendix A gives qualitatively the
performance characteristics as a measure of cost for commonly used 1C logic families.

6.1.4 Part Numbering Systems
Typically, parts in data books are given specific part numbers indicative of the logic func-
tion they perform and the logic family to which they belong. Commercially available digital
devices belonging to the CMOS and TTL (transistor-transistor logic} families are given
the part prefix "74xnnn", where the "x" represents a string of literals indicating the logic
family or subfamily and "nnn" is the part number. To understand this nomenclature the
following literals are defined: H = High-speed, L = Low-power, A = Advanced, F = Fast,
C = CMOS, and S = Schottky. For example, 74HCOO is a two-input high-speed CMOS
NAND gate and a 74AS27 is a three-input advanced Schottky NOR gate. To avoid referring
to any specific logic family or subfamily, the "x" descriptor is used along with the part
number. For example, a 74x151 is an 8-to-l multiplexer of a generic type, meaning that it
belongs to any of the families for which the prefix "74 • • •" is applicable. The TTL subfam-
ilies designated 74nnn, 74Lnnn, and 74Hnnn have been made obsolete by the presence of
modern Schottky subfamilies.
Another member of the bipolar family is called ECL for emitter-coupled logic. The
ECL family is currently the fastest of the logic families but has an extremely high power
consumption and high PDF. ECL parts are named either with a 5-digit number system
(lOnnn) or a 6-digit system (lOOnnn), depending on which subfamily is being referenced.
In either case all part numbers "nnn" are always three digits in length, unlike those for
CMOS and TTL families, which can be two or three digits in length. Appendix A quali-
tatively summarizes the performance characteristics of TTL, ECL, NMOS, and CMOS
families.

6.1.5 Design Procedure
The design of any combinational logic device generally begins with the description of
and specifications for the device and ends with a suitable logic implementation. To